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authorPatrick Williams <iawillia@us.ibm.com>2011-07-15 15:35:41 -0500
committerA. Patrick Williams III <iawillia@us.ibm.com>2011-07-25 15:47:45 -0500
commitb679a1729d7aea0870544e886ddb4b03e1ecf4c4 (patch)
tree8b945be92f740a9719a70465df5d8ceb635f5f95 /src/include
parentff7d0cf68fab49bb965467bcd9a6a8068e799349 (diff)
downloadtalos-hostboot-b679a1729d7aea0870544e886ddb4b03e1ecf4c4.tar.gz
talos-hostboot-b679a1729d7aea0870544e886ddb4b03e1ecf4c4.zip
Reduce working threads to first core.
This is required to reduce the memory footprint of the kernel so we can fit within 2MB. This patch will cause (in simics) all other cores/threads to execute a 'doze' instruction and cease executing. In VBU, only 1 core will be active anyhow. Change-Id: If1bdc01393b02d802ba7595a88dcf3331efc2d4e Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/203 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Diffstat (limited to 'src/include')
-rw-r--r--src/include/kernel/cpuid.H74
1 files changed, 74 insertions, 0 deletions
diff --git a/src/include/kernel/cpuid.H b/src/include/kernel/cpuid.H
new file mode 100644
index 000000000..fa9b0649b
--- /dev/null
+++ b/src/include/kernel/cpuid.H
@@ -0,0 +1,74 @@
+#ifndef __KERNEL_CPUID_H
+#define __KERNEL_CPUID_H
+
+#include <arch/ppc.H>
+
+/** @enum ProcessorCoreType
+ * @brief Enumeration of the different supported processor cores.
+ */
+enum ProcessorCoreType
+{
+ /** Base Power7 */
+ POWER7,
+ /** Power7+ */
+ POWER7_PLUS,
+
+ /** Power8 "Salerno" (low-end) core */
+ POWER8_SALERNO,
+ /** Power8 "Venice" (high-end) core */
+ POWER8_VENICE,
+
+ UNKNOWN,
+};
+
+/** @fn getCpuType()
+ * @brief Decode the processor type from the PVR register.
+ *
+ * These values come from the pervasive spec for each processor.
+ *
+ * @return ProcessorCoreType - Value from enumeration for this core.
+ */
+ALWAYS_INLINE
+ProcessorCoreType getCpuType()
+{
+ uint64_t l_pvr = getPVR();
+
+ // Layout of the PVR is (32-bit):
+ // 2 nibbles reserved.
+ // 2 nibbles chip type.
+ // 1 nibble technology.
+ // 1 nibble major DD.
+ // 1 nibble reserved.
+ // 1 nibble minor DD.
+
+ switch(l_pvr & 0xFFFF0000)
+ {
+ case 0x003F0000:
+ return POWER7;
+
+ case 0x004A0000:
+ return POWER7_PLUS;
+
+ case 0x004B0000:
+ return POWER8_VENICE;
+
+ default:
+ return UNKNOWN;
+ }
+}
+
+/** @fn getCpuDD
+ * @brief Decode the processor DD level from the PVR register.
+ *
+ * These offsets come from the pervasive spec for each processor.
+ *
+ * @return 1 byte DD level as <major nibble, minor nibble>.
+ */
+ALWAYS_INLINE
+uint8_t getCpuDD()
+{
+ uint64_t l_pvr = getPVR();
+ return ((l_pvr & 0x0F00) >> 4) | (l_pvr & 0x000F);
+}
+
+#endif
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