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| author | Mike Baiocchi <mbaiocch@us.ibm.com> | 2018-07-03 09:29:59 -0500 |
|---|---|---|
| committer | William G. Hoffa <wghoffa@us.ibm.com> | 2018-07-06 23:26:48 -0400 |
| commit | a76fe8f24e07ab143cdd8591983c12925eae281a (patch) | |
| tree | 6fea8349987aeed1ab8d84af47a246735eb575a3 /src/include | |
| parent | ea5c84fe7741f94fb1198483f9e833fcaae202e5 (diff) | |
| download | talos-hostboot-a76fe8f24e07ab143cdd8591983c12925eae281a.tar.gz talos-hostboot-a76fe8f24e07ab143cdd8591983c12925eae281a.zip | |
Read HW Key Hash From SBE Seeprom via ChipOp when applicable
This commit uses SBEIO ChipOps to read the HW Key Hash from the
SBE Seeprom when reading from the Seeprom that booted the processor.
This will help avoid I2C collisions when both Hostboot and the SBE
try to access the same SBE Seeprom at the same time.
Change-Id: I5693cc59aa2a7259f07363328bd8513c943f0a06
CQ:SW435288
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61958
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/usr/sbe/sbe_common.H | 1 | ||||
| -rw-r--r-- | src/include/usr/sbe/sbe_update.H | 1 | ||||
| -rw-r--r-- | src/include/usr/sbe/sbeif.H | 10 | ||||
| -rw-r--r-- | src/include/usr/sbeio/sbeioif.H | 9 |
4 files changed, 18 insertions, 3 deletions
diff --git a/src/include/usr/sbe/sbe_common.H b/src/include/usr/sbe/sbe_common.H index 359335e66..15f623c24 100644 --- a/src/include/usr/sbe/sbe_common.H +++ b/src/include/usr/sbe/sbe_common.H @@ -158,6 +158,7 @@ namespace SBE static_assert(0 == (sizeof(sbeSeepromVersionInfo_t) % 8), "sbeSeepromVersionInfo_t is not 8-byte-aligned"); + typedef uint8_t sbe_image_version_t[SBE_IMAGE_VERSION_SIZE]; /** * @brief Struct of individual SBE entry in SBE diff --git a/src/include/usr/sbe/sbe_update.H b/src/include/usr/sbe/sbe_update.H index 82b535ddc..d907e57c9 100644 --- a/src/include/usr/sbe/sbe_update.H +++ b/src/include/usr/sbe/sbe_update.H @@ -26,7 +26,6 @@ #define __SBE_SBE_UPDATE_H #include <sbe/sbe_common.H> // sbeSeepromVersionInfo_t -#include <sbe/sbeif.H> // sbe_image_version_t #include <stdint.h> // uint32_t, etc #include <errl/errlentry.H> // errlHndl_t diff --git a/src/include/usr/sbe/sbeif.H b/src/include/usr/sbe/sbeif.H index 1768f2aa9..0a5985253 100644 --- a/src/include/usr/sbe/sbeif.H +++ b/src/include/usr/sbe/sbeif.H @@ -26,6 +26,7 @@ #define _SBEIF_H #include <sbe/sbe_common.H> +#include <sbe/sbe_update.H> #include <errl/errlentry.H> #include <pnor/pnorif.H> #include <secureboot/service.H> @@ -33,8 +34,6 @@ namespace SBE { - typedef uint8_t sbe_image_version_t[SBE_IMAGE_VERSION_SIZE]; - /** * @brief Gets a pointer to the proper SBE image in PNOR * @@ -115,6 +114,12 @@ namespace SBE * NOTE: Ignored if i_image_ptr specifies an image * (ie, != nullptr). * + * + * @param[in] i_bootSide Designates which Seeprom the processor booted on. + * If i_bootSide and i_seeprom match then ChipOps + * will be used to read the Seeprom to avoid I2C + * collisions. + * * @param[out] o_hash HW Key Hash returned from the Processor SEEPROM * * @param[in] i_image_ptr Defaults to nullptr. @@ -127,6 +132,7 @@ namespace SBE */ errlHndl_t getHwKeyHashFromSbeImage(TARGETING::Target* i_target, EEPROM::eeprom_chip_types_t i_seeprom, + sbeSeepromSide_t i_bootSide, SHA512_t o_hash, const void * i_image_ptr = nullptr); diff --git a/src/include/usr/sbeio/sbeioif.H b/src/include/usr/sbeio/sbeioif.H index 0f879de92..f42278911 100644 --- a/src/include/usr/sbeio/sbeioif.H +++ b/src/include/usr/sbeio/sbeioif.H @@ -27,6 +27,12 @@ #include <errl/errlentry.H> + +/* Associated defines for sendPsuReadSeeprom() function below */ +#define CHIPOP_READ_SEEPROM_SIZE_ALIGNMENT_BYTES 128 +#define CHIPOP_READ_SEEPROM_DEST_ADDR_ALIGNMENT_BYTES 8 + + namespace SBEIO { enum KeyAddrStashKeys @@ -310,11 +316,14 @@ namespace SBEIO * @brief Sends a PSU chipOp to request Seeprom read from SBE * * @param[in] i_target Target with SBE to send read request to + * Assert if i_target == nullptr * @param[in] i_seepromOffset Offset in the seeprom image where we want * to start copying from (ignores ECC) * @param[in] i_readSize Amount of bytes we want to copy (ignores ECC) + * Assert if i_readSize is not 128-byte-aligned * @param[in] i_destAddr Address that hostboot has prepared which the * sbe will write too + * Assert if i_destAddr is not 8-byte aligned * @param[out] o_opSupported Bool which tells us if the sbe supports the * chipOp or not * |

