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author | Mike Baiocchi <mbaiocch@us.ibm.com> | 2017-11-10 09:57:21 -0600 |
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committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-11-17 09:25:29 -0500 |
commit | 8f6cf7d7310dd8980dd1abca6692ed1c59111f62 (patch) | |
tree | 47d3d78350a388a90a31c30b5fb187d987930897 /src/include | |
parent | 663aae09de4001c7d17225f44ae824215e459bc7 (diff) | |
download | talos-hostboot-8f6cf7d7310dd8980dd1abca6692ed1c59111f62.tar.gz talos-hostboot-8f6cf7d7310dd8980dd1abca6692ed1c59111f62.zip |
Add TCE Support to utillidmgr
This commit looks to see if the system is using TCEs and then
uses them in the utillidmgr. There were also some updates to the
TCE interfaces to allow for this support.
Change-Id: Iccaf0137c2924d3f3806fee1a8068ba2e23cb7d2
RTC:68295
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49530
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Marshall J. Wilks <mjwilks@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-by: Stephen M. Cprek <smcprek@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/include')
-rw-r--r-- | src/include/usr/util/utiltce.H | 22 |
1 files changed, 14 insertions, 8 deletions
diff --git a/src/include/usr/util/utiltce.H b/src/include/usr/util/utiltce.H index f71946fee..0aaffacf1 100644 --- a/src/include/usr/util/utiltce.H +++ b/src/include/usr/util/utiltce.H @@ -45,34 +45,40 @@ namespace TCE * @param[in] i_startingAddress - Starting physical address that the allocated * TCEs will map to. * Needs to be Page-Aligned or will fail. + * * @param[in] i_size - Size of the address space that TCEs map to. * Size must be less than (512K * PAGESIZE) or will fail. * Assert if not greater than zero. * + * @param[out] o_startingToken - Starting Entry into the table. + * (This is an offset into the array based on the + * TCE index * PAGESIZE. Each TCE entry maps to + * a pagesize of memory) + * * Note: First time this is called will cause TCE Table to be created and * the Processors to be setup to point at the TCE Table * * @return errlHndl_t - Return Error Handle if failed * */ -errlHndl_t utilAllocateTces(uint64_t i_startingAddress, - size_t i_size); +errlHndl_t utilAllocateTces(uint64_t i_startingAddress, + size_t i_size, + uint32_t& o_startingToken); /** * @brief Responsible for deallocating TCEs * - * @param[in] i_startingAddress Starting physical address of the TCEs that - * are to be deallocated from the TCE Table. - * Needs to be page-aligned or will fail. - * @param[in] i_size - Size of address space that the TCEs that are to - * be deallocated map to. + * @param[in] i_startingToken Token indicating the starting entry of the + * TCE Table to remove + * + * @param[in] i_size - Size of memory space to remove associated TCE entries * Size must be less than (512K * PAGESIZE) or will fail. * Assert if not greater than zero. * * @return errlHndl_t - Return Error Handle if failed * */ -errlHndl_t utilDeallocateTces(uint64_t i_startingAddress, +errlHndl_t utilDeallocateTces(uint32_t i_startingToken, size_t i_size); |