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author | Patrick Williams <iawillia@us.ibm.com> | 2010-09-14 18:09:10 -0500 |
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committer | Patrick Williams <iawillia@us.ibm.com> | 2010-09-14 18:09:10 -0500 |
commit | 7dbf41357d6061170530601022c123eaf8fc2934 (patch) | |
tree | 8da74fbf3a1919c73403b1c67ae8edad77843790 /src/include | |
parent | 2bc4d154dd12ccd2280012ddb1439020ca79eb79 (diff) | |
download | talos-hostboot-7dbf41357d6061170530601022c123eaf8fc2934.tar.gz talos-hostboot-7dbf41357d6061170530601022c123eaf8fc2934.zip |
Various VMM updates.
1) Do SLBIA prior to creating initial SLB entry.
2) Do proper TLBIEs.
3) Set Ks/Kp in SLB properly.
4) Test data storage exception on code space.
Diffstat (limited to 'src/include')
-rw-r--r-- | src/include/kernel/vmmmgr.H | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/include/kernel/vmmmgr.H b/src/include/kernel/vmmmgr.H index a8bb5ae3f..adf699e85 100644 --- a/src/include/kernel/vmmmgr.H +++ b/src/include/kernel/vmmmgr.H @@ -93,6 +93,24 @@ class VmmManager pte.a &= ~0x01; pte.a |= (valid ? 0x1 : 0x0); + + if (!valid) + { + asm volatile("ptesync" ::: "memory"); + + register uint64_t rS = 0, rB = 0; + rB = (getTid(pte) << 11) // VA[0:54). + | (((uint64_t)&pte) & 0x3FF8) >> 7; // VA[55:65]. + rB <<= 12; // Put in rB[0:51]. + rB |= 0x0100; // B = 01 (1TB). + + // TLBIE isn't correct in gcc, hand code asm. + asm volatile(".long 0x7c000264 | (%0 << 11) | (%1 << 21)" :: + "r"(rB), "r"(rS) : "memory"); + + asm volatile("eieio" ::: "memory"); + asm volatile("tlbsync" ::: "memory"); + } asm volatile("ptesync" ::: "memory"); } |