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| author | Dean Sanner <dsanner@us.ibm.com> | 2016-10-17 17:58:45 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-10-19 18:48:13 -0400 |
| commit | 431b1fe7e5a66fa9eab5b9930ca2acbb4df5a25a (patch) | |
| tree | caf7ebd2343beb8404400c6debec085c8d26f002 /src/include | |
| parent | 3ebbca6ad64f2d02e6cb906c128f8e9e49aa69d9 (diff) | |
| download | talos-hostboot-431b1fe7e5a66fa9eab5b9930ca2acbb4df5a25a.tar.gz talos-hostboot-431b1fe7e5a66fa9eab5b9930ca2acbb4df5a25a.zip | |
Handle ioppe in Xbus PG field
Based on Partial Good v9 the ioppe was added to xbus
and xbus is the pbiox regions not iox
Change-Id: I65384c542eb86d57f11bb77c9a4f6ef0a8cf757c
CMVC-Coreq: 1008809
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31431
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/usr/hwas/common/hwasCommon.H | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/include/usr/hwas/common/hwasCommon.H b/src/include/usr/hwas/common/hwasCommon.H index f381beb5a..b2f896d81 100644 --- a/src/include/usr/hwas/common/hwasCommon.H +++ b/src/include/usr/hwas/common/hwasCommon.H @@ -158,15 +158,15 @@ const uint32_t VPD_CP00_PG_N3_NPU = 0x0100; const uint32_t VPD_CP00_PG_N3_MCS01 = 0x0020; const uint32_t VPD_CP00_PG_XBUS_INDEX = 6; -// all good - 3:VITAL, 4:PRV, 5:IOX0*+, 6:IOX1+, 7:IOX2+, -// 8:PBIOX0*, 9:PBIOX1, 10:PBIOX2, 14:PLLIOX +// all good - 3:VITAL, 4:PRV, 5:IOX0*, 6:IOX1, 7:IOX2, 8:IOPPE +// 9:PBIOX0*+, 10:PBIOX1+, 11:PBIOX2+, 14:PLLIOX // Nimbus doesn't physically have PBIOX0 and IOX0. IOX0 is // taken care of by xbus links, need to handle PBIOX0 as part of -// the full chiplet good -const uint32_t VPD_CP00_PG_XBUS_GOOD_NIMBUS = 0xE09D; -const uint32_t VPD_CP00_PG_XBUS_GOOD_CUMULUS= 0xE01D; -const uint32_t VPD_CP00_PG_XBUS_PG_MASK = 0x0700; -const uint32_t VPD_CP00_PG_XBUS_IOX[3] = {0x0400, 0x0200, 0x0100}; +// the full chiplet good, so full good is E40D instead of E44D +const uint32_t VPD_CP00_PG_XBUS_GOOD_NIMBUS = 0xE40D; +const uint32_t VPD_CP00_PG_XBUS_GOOD_CUMULUS= 0xE00D; +const uint32_t VPD_CP00_PG_XBUS_PG_MASK = 0x0070; +const uint32_t VPD_CP00_PG_XBUS_IOX[3] = {0x0040, 0x0020, 0x0010}; const uint32_t VPD_CP00_PG_MCxx_INDEX[4] = {7, 7, 8, 8}; // by MCS // all good - 3:VITAL, 4:PRV, 5:MCA01, 6:IOM01+, 7:IOM23+, 14:PLLMEM |
