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author | Jaymes Wilks <mjwilks@us.ibm.com> | 2018-06-14 09:26:30 -0500 |
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committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-06-28 22:47:58 -0400 |
commit | ef1e2276640040b2bbf187a1d85c8bd6929f4d56 (patch) | |
tree | a34b2c4d647e3f047a8fed78f30596b548edbcb2 /src/include/usr | |
parent | cf258fcfb753bafcfac0659ded5f312c793d047d (diff) | |
download | talos-hostboot-ef1e2276640040b2bbf187a1d85c8bd6929f4d56.tar.gz talos-hostboot-ef1e2276640040b2bbf187a1d85c8bd6929f4d56.zip |
In non-MNFG, only match SBE keys for the sides that boot
FSP was not IPL'ing from SBE side 1 when production key is corrupt
in SEEPROM of SBE side 0 (due to the key mismatch check). This
change gets around that by only matching SBE keys for the sides
that booted in non-MNFG case.
Change-Id: I1dfcb5c7f7e281125fdbcfc8b8f3a84747c90f59
CQ:SW420430
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60571
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
Reviewed-by: ILYA SMIRNOV <ismirno@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/include/usr')
-rw-r--r-- | src/include/usr/isteps/istep_reasoncodes.H | 4 | ||||
-rw-r--r-- | src/include/usr/sbe/sbe_update.H | 7 |
2 files changed, 9 insertions, 2 deletions
diff --git a/src/include/usr/isteps/istep_reasoncodes.H b/src/include/usr/isteps/istep_reasoncodes.H index 31bb8a7bb..282ebe3c3 100644 --- a/src/include/usr/isteps/istep_reasoncodes.H +++ b/src/include/usr/isteps/istep_reasoncodes.H @@ -54,7 +54,7 @@ namespace ISTEP MOD_PM_LOAD_HOST_DATA_TO_SRAM = 0x12, MOD_VOLTAGE_CONFIG = 0x13, MOD_PM_VERIFY_OCC_CHKPT = 0x14, - MOD_UPDATE_REDUNDANT_TPM = 0x15, + MOD_VALIDATE_SECURITY_SETTINGS = 0x15, MOD_PROC_EXIT_CACHE_CONTAINED = 0x16, MOD_SBE_PERFORM_UPDATE_CHECK = 0x1A, MOD_SET_IPL_PARMS = 0x1D, @@ -127,6 +127,8 @@ namespace ISTEP RC_ULTRA_TURBO_FREQ_MISMATCH = ISTEP_COMP_ID | 0x45, RC_NEST_FREQ_MISMATCH = ISTEP_COMP_ID | 0x46, RC_NO_VALID_MEM_CONFIG = ISTEP_COMP_ID | 0x47, + RC_MASTER_GET_SBE_BOOT_SEEPROM_FAIL = ISTEP_COMP_ID | 0x48, + RC_SLAVE_GET_SBE_BOOT_SEEPROM_FAIL = ISTEP_COMP_ID | 0x49, }; }; diff --git a/src/include/usr/sbe/sbe_update.H b/src/include/usr/sbe/sbe_update.H index 70ecf6f15..82b535ddc 100644 --- a/src/include/usr/sbe/sbe_update.H +++ b/src/include/usr/sbe/sbe_update.H @@ -317,10 +317,15 @@ namespace SBE * * @param[out] o_bootSide The Seeprom the SBE booted from * + * @param[in] i_failoverToMaster If the SBE is not started for the supplied + * processor, use master processor instead. + * default is true + * * @return errlHndl_t Error log handle on failure. */ errlHndl_t getSbeBootSeeprom(TARGETING::Target* i_target, - sbeSeepromSide_t& o_bootSide); + sbeSeepromSide_t& o_bootSide, + bool i_failoverToMaster = true); /** * @brief Collects Version information from a specific SEEPROM using I2C |