Add EEPROM caching device op

This commit introduces a new EEPROM_CACHE deviceOp and registers
the OCMB_CHIP, PROC, and DIMM targets to it. This is part of the
larger effort to transition for a "VPD" cache to an "EEPROM" cache
in pnor. The deviceOp is currently called in hwasPlat's
platPresenceDetect if the target in question has a
ATTR_EEPROM_VPD_PRIMARY_INFO associated with it. The layout for the
new EECACHE section in pnor is defined in eepromCache_const.H.
Essentially it is a header that contains an array of record headers
that tell where in the EECACHE pnor section a given cached EEPROM
can be found. All EEPROM targets will be allocated space in the
EECACHE section but only present targets will have their cache
filled in.

RTC: 196805
Change-Id: I49c341c9784be04ddf0259bd444f06c9baf8c6f1
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70520
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: Roland Veloz <rveloz@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

3 files changed, 112 insertions, 25 deletions

diff --git a/src/include/usr/devicefw/userif.H b/src/include/usr/devicefw/userif.H
index cf00cfee1..523537cfb 100644
--- a/src/include/usr/devicefw/userif.H
+++ b/src/include/usr/devicefw/userif.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2018                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2019                        */
 /* [+] Google Inc.                                                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
@@ -49,29 +49,30 @@ namespace DeviceFW
 
     enum AccessType
     {
-        SCOM = 0,  // SCOM registers
-        PNOR,      // PNOR flash
-        MAILBOX,   // FSP mailbox
-        PRESENT,   // Presence detection
-        FSI,       // FSI/CFAM registers
-        SPD,       // Serial Presence Detect Data for JEDEC DIMMs
-        MVPD,      // Module (processor) VPD
-        CVPD,      // Centaur (memory buffer) VPD
-        SCAN,      // Scan rings
-        EEPROM,    // Standard EEPROM/SEEPROM over i2c
-        GPIO,      // GPIO registers
-        LPC,       // Low Pin Count bus
-        IPMIBT,    // As opposed to other phy's
-        PVPD,      // Planar VPD
-        TPM,       // Trusted Platform Module
-        SIO,       // BMC Super I/O registers
-        AHB_SIO,   // AST Hostbridge via SIO
-        DVPD,      // Direct access memory VPD
-        NODECOMM,  // Internode communication
-        NVDIMM,    // Non-volatile DIMM controller access
-        FAPI_I2C,  // FAPI2-triggered i2c accesses
-        MMIO,      // Memory Mapped I/O
-        IDEC,      // Read and set EC and CHIPID values
+        SCOM = 0,     // SCOM registers
+        PNOR,         // PNOR flash
+        MAILBOX,      // FSP mailbox
+        PRESENT,      // Presence detection
+        FSI,          // FSI/CFAM registers
+        SPD,          // Serial Presence Detect Data for JEDEC DIMMs
+        MVPD,         // Module (processor) VPD
+        CVPD,         // Centaur (memory buffer) VPD
+        SCAN,         // Scan rings
+        EEPROM,       // Standard EEPROM/SEEPROM over i2c
+        GPIO,         // GPIO registers
+        LPC,          // Low Pin Count bus
+        IPMIBT,       // As opposed to other phy's
+        PVPD,         // Planar VPD
+        TPM,          // Trusted Platform Module
+        SIO,          // BMC Super I/O registers
+        AHB_SIO,      // AST Hostbridge via SIO
+        DVPD,         // Direct access memory VPD
+        NODECOMM,     // Internode communication
+        NVDIMM,       // Non-volatile DIMM controller access
+        FAPI_I2C,     // FAPI2-triggered i2c accesses
+        MMIO,         // Memory Mapped I/O
+        IDEC,         // Read and set EC and CHIPID values
+        EEPROM_CACHE, // Read EEPROM over I2C and write to PNOR
         LAST_ACCESS_TYPE,
     };
 
@@ -124,6 +125,13 @@ namespace DeviceFW
     #define DEVICE_PRESENT_ADDRESS() \
         DeviceFW::PRESENT
 
+    /** Construct the device addressing parameters for the EEPROM_CACHE device ops.
+    *  @param[in] i_present indicates if target is present or not.
+    *  @param[in] i_eepromType indicates which EEPROM we wish to cache (PRIMARY/BACKUP etc)
+    */
+    #define DEVICE_CACHE_EEPROM_ADDRESS(i_present, i_eepromType) \
+        DeviceFW::EEPROM_CACHE, static_cast<uint64_t>((i_present)), static_cast<uint64_t>((i_eepromType))
+
     /**
      * Construct a PNOR DD address
      *    address = 0000_0000_0000_000c_aaaa_aaaa_aaaa_aaaa
diff --git a/src/include/usr/i2c/eepromCache_const.H b/src/include/usr/i2c/eepromCache_const.H
new file mode 100644
index 000000000..e94798b79
--- /dev/null
+++ b/src/include/usr/i2c/eepromCache_const.H
@@ -0,0 +1,73 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/include/usr/i2c/eepromCache_const.H $                     */
+/*                                                                        */
+/* OpenPOWER HostBoot Project                                             */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2019                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef EEPROM_CACHE_CONST_H
+#define __EEPROM_CACHE_CONST_H
+
+constexpr uint8_t MAX_EEPROMS_VERSION_1 = 50;
+constexpr uint8_t INVALID_EEPROM_INDEX  = 0xFF;
+constexpr uint32_t UNSET_INTERNAL_OFFSET_VALUE = 0xFFFFFFFF;
+constexpr uint32_t UNSET_END_OF_CACHE_VALUE = UNSET_INTERNAL_OFFSET_VALUE;
+
+enum EECACHE_VERSION
+{
+    EECACHE_VERSION_UNSET   = 0xFF,
+    EECACHE_VERSION_1       = 0x01,
+    EECACHE_VERSION_LATEST  = EECACHE_VERSION_1,
+};
+
+enum EEPROM_ATTRIBUTE_MASK : uint8_t
+{
+  HAS_EEPROM_NV_INFO           = 0x01,
+  HAS_EEPROM_SBE_BACKUP_INFO   = 0x02,
+  HAS_EEPROM_SBE_PRIMARY_INFO  = 0x04,
+  HAS_EEPROM_VPD_BACKUP_INFO   = 0x08,
+  HAS_EEPROM_VPD_PRIMARY_INFO  = 0x10,
+};
+
+
+struct eepromRecordHeader
+{
+    uint32_t target_huid;
+    uint8_t  port;
+    uint8_t  engine;
+    uint8_t  devAddr;
+    uint32_t mux_huid;
+    uint8_t  mux_select;
+    uint32_t record_size;
+    uint32_t internal_offset;
+    uint8_t  record_valid;
+} PACKED ;
+                                                                    //record_size      // internal_offset //record_valid
+constexpr size_t RECORD_COMPARE_SIZE = sizeof(eepromRecordHeader) - sizeof(uint32_t) - sizeof(uint32_t) - sizeof(uint8_t);
+
+struct eecacheSectionHeader
+{
+    uint8_t version;
+    uint32_t end_of_cache;
+    eepromRecordHeader recordHeaders[MAX_EEPROMS_VERSION_1];
+} PACKED ;
+
+
+#endif
\ No newline at end of file
diff --git a/src/include/usr/i2c/i2creasoncodes.H b/src/include/usr/i2c/i2creasoncodes.H
index 6b08aefc2..a723e4ec8 100644
--- a/src/include/usr/i2c/i2creasoncodes.H
+++ b/src/include/usr/i2c/i2creasoncodes.H
@@ -66,6 +66,8 @@ enum i2cModuleId
     READ_I2C_ATTRIBUTES                 = 0x10,
     I2C_ACCESS_MUX                      = 0x11,
     I2C_GENERIC_PRES_DETECT             = 0x12,
+    I2C_CACHE_EEPROM                    = 0x13,
+    I2C_CLEAR_EECACHE                   = 0x14,
 };
 
 
@@ -101,7 +103,11 @@ enum i2cReasonCode
     I2C_MUX_TARGET_NON_FUNCTIONAL        = I2C_COMP_ID | 0x15,   // The MUX target is non functional
     I2C_INVALID_LENGTH                   = I2C_COMP_ID | 0x16,   // Invalid data buffer length passed to function
     I2C_NULL_MASTER_TARGET               = I2C_COMP_ID | 0x17,   // Target Service's toPath() returned nullptr for target
-};
+    I2C_FAILED_TO_FLUSH_CONTENTS         = I2C_COMP_ID | 0x18,   // Error occured while trying to flush the mmio pages out
+                                                                 // containing contents of an EEPROM's cached data in the EECACHE
+                                                                 // PNOR section
+    I2C_FAILED_TO_FLUSH_HEADER           = I2C_COMP_ID | 0x19,   // Error occured while trying to flush the mmio page out
+};                                                               // containing EECACHE header the to pnor
 
 
 enum UserDetailsTypes