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| author | Matthew Raybuck <matthew.raybuck@ibm.com> | 2019-04-17 12:53:31 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2019-05-01 09:05:04 -0500 |
| commit | 5f68c549965e0cebcb557026938ba57ff0aa8ba8 (patch) | |
| tree | ff7d8613a33318ac2a0f2e0f61646facd94ae575 /src/include/usr | |
| parent | decb0b6a03b108af9f5818ebd9dc7f95b3ce342b (diff) | |
| download | talos-hostboot-5f68c549965e0cebcb557026938ba57ff0aa8ba8.tar.gz talos-hostboot-5f68c549965e0cebcb557026938ba57ff0aa8ba8.zip | |
Gemini vs Explorer Presence Detection via SPD
Since the OCMB chip is held in reset until after presence detection the
IDEC register cannot be read to differentiate between Gemini and
Explorer chip types. To work around this issue, during the early part of
IPL when presence detection is occurring the OCMB IDEC function will instead
read the SPD and populate the necessary attributes with what is found
there. That will be used to determine the difference between Gemini and
Explorer until later when the OCMB IDEC register can be read from. At
that point the IDEC read will be executed again and the data read from
the OCMB IDEC register will be used to cross-check the data read from
the SPD. Any discrepancies will be handled with predictive error logs.
Change-Id: Ica664b06ff3488f48253d3ef02eff2d49c5d240d
RTC: 208696
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76108
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/include/usr')
| -rw-r--r-- | src/include/usr/hwas/common/hwas_reasoncodes.H | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/include/usr/hwas/common/hwas_reasoncodes.H b/src/include/usr/hwas/common/hwas_reasoncodes.H index 7b4b0cd39..f2d4e0da0 100644 --- a/src/include/usr/hwas/common/hwas_reasoncodes.H +++ b/src/include/usr/hwas/common/hwas_reasoncodes.H @@ -43,6 +43,9 @@ namespace HWAS MOD_UPDATE_PROC_COMPAT_RISK_LEVEL = 0x0C, MOD_CHECK_PG_FOR_DESC = 0x0D, MOD_OCMB_IDEC = 0x0E, + MOD_OCMB_IDEC_PHASE_1 = 0x0F, + MOD_OCMB_IDEC_PHASE_2 = 0x10, + MOD_OCMB_TRANSLATE_SPD_IDEC = 0x11, }; enum HwasReasonCode @@ -81,8 +84,11 @@ namespace HWAS RC_FORCED_NATIVE_INVALID_MIXED_EC = HWAS_COMP_ID | 0x1C, RC_FORCED_NATIVE_OF_INCOMPATIBLE_RISK = HWAS_COMP_ID | 0x1D, RC_PARTIAL_GOOD_MISSING_TARGET = HWAS_COMP_ID | 0x1E, - RC_OCMB_SPD_IDEC_MISMATCH = HWAS_COMP_ID | 0x1F, + RC_OCMB_SPD_REVISION_MISMATCH = HWAS_COMP_ID | 0x1F, RC_OCMB_UNEXPECTED_IDEC = HWAS_COMP_ID | 0x20, + RC_OCMB_UNKNOWN_CHIP_TYPE = HWAS_COMP_ID | 0x21, + RC_OCMB_INTERFACE_TYPE_MISMATCH = HWAS_COMP_ID | 0x22, + RC_OCMB_CHIP_ID_MISMATCH = HWAS_COMP_ID | 0x23, }; enum HwasPlatUserDetailsTypes |
