UCD Flash Update: Support I2C SMBUS operations for UCD flash update

- Adds I2C SMBUS operations for UCD flash update
- Creates UCD component ID + trace name
- Creates stub for UCD flash update entry point

Change-Id: Id75cdd137b5a4924998c04bdbdce9218610a4906
RTC: 201992
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72229
Reviewed-by: Ilya Smirnov <ismirno@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matthew Raybuck <matthew.raybuck@ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

6 files changed, 199 insertions, 28 deletions

diff --git a/src/include/usr/devicefw/driverif.H b/src/include/usr/devicefw/driverif.H
index 6e94f04e4..e91c43518 100644
--- a/src/include/usr/devicefw/driverif.H
+++ b/src/include/usr/devicefw/driverif.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2018                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2019                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -91,6 +91,20 @@ namespace DeviceFW
         WILDCARD = -1,
     };
 
+    /**
+     *  @brief Enum indicating which type of I2C sub-operation
+     *     to perform
+     */
+    enum I2C_SUBOP : uint64_t
+    {
+        I2C_STANDARD           = 0, ///< Traditional I2C
+        I2C_PAGE_OP            = 1, ///< Page operation
+        I2C_SMBUS_BLOCK        = 2, ///< I2c SMBUS Block Read/Write
+        I2C_SMBUS_WORD         = 3, ///< I2c SMBUS Read/Write Word
+        I2C_SMBUS_BYTE         = 4, ///< I2c SMBUS Read/Write Byte
+        I2C_SMBUS_SEND_OR_RECV = 5, ///< I2c SMBUS Send/Receive Byte
+    };
+
 #ifndef PARSER
     /** Construct the device addressing parameters for FSISCOM device ops.
      *  @param[in] i_address - FSISCOM address to operate on.
@@ -130,6 +144,7 @@ namespace DeviceFW
      */
     #define DEVICE_I2C_PARMS(port, engine, devAddr, offset_len,\
                              offset, muxSelector, i_i2cMuxPath)\
+        static_cast<uint64_t>( DeviceFW::I2C_STANDARD ),\
         static_cast<uint64_t>( port ),\
         static_cast<uint64_t>( engine ),\
         static_cast<uint64_t>( devAddr ),\
@@ -139,6 +154,33 @@ namespace DeviceFW
         static_cast<const TARGETING::EntityPath*>(i_i2cMuxPath)
 
     /**
+     * @brief Macro that handles the I2C SMBUS data transfers that use
+     *     a command code (Read/Write Word/Byte or Block Read/Write)
+     */
+    #define I2C_SMBUS_RW_W_CMD_PARAMS(i_subop,i_engine,i_port,i_devAddr,\
+                 i_commandCode,i_muxSelector,i_i2cMuxPath)\
+        static_cast<uint64_t>(i_subop),\
+        static_cast<uint64_t>(i_port),\
+        static_cast<uint64_t>(i_engine),\
+        static_cast<uint64_t>(i_devAddr),\
+        static_cast<uint64_t>(i_commandCode),\
+        static_cast<uint64_t>(i_muxSelector),\
+        static_cast<const TARGETING::EntityPath*>(i_i2cMuxPath)
+
+    /**
+     * @brief Macro that handles the I2C SMBUS data transfers that don't use
+     *     a command code byte (Send/Receive Byte)
+     */
+    #define I2C_SMBUS_RW_WO_CMD_PARAMS(i_subop,i_engine,i_port,i_devAddr,\
+                                   i_muxSelector,i_i2cMuxPath)\
+        static_cast<uint64_t>(i_subop),\
+        static_cast<uint64_t>(i_port),\
+        static_cast<uint64_t>(i_engine),\
+        static_cast<uint64_t>(i_devAddr),\
+        static_cast<uint64_t>(i_muxSelector),\
+        static_cast<const TARGETING::EntityPath*>(i_i2cMuxPath)
+
+    /**
      * Construct the device addressing parameters for the I2C device ops.
      * @param[in] i_port - Which port to use from the I2C master.
      * @param[in] i_engine - Which I2C master engine to use.
@@ -153,6 +195,53 @@ namespace DeviceFW
                                 0, nullptr, i_i2cMuxBusSelector, i_i2cMuxPath)
 
     /**
+     *  @brief Construct the device addressing parameters for the I2C SMBUS
+     *      data transfer commands that have a command parameter
+     *
+     *  @param[in] i_engine Which I2C master engine to use
+     *  @param[in] i_port Which port to use from the I2C master engine above
+     *  @param[in] i_devAddr The device address to communicate with on a given
+     *      engine/port.
+     *  @param[in] i_commandCode The PMBUS command to execute
+     *  @param[in] i_i2cMuxBusSelector The I2C MUX bus selector
+     *  @param[in] i_i2cMuxPath The I2C MUX entity path
+     */
+    #define DEVICE_I2C_SMBUS_BLOCK(i_engine,i_port,i_devAddr,i_commandCode,\
+                                   i_i2cMuxBusSelector,i_i2cMuxPath)\
+        DeviceFW::I2C, I2C_SMBUS_RW_W_CMD_PARAMS(DeviceFW::I2C_SMBUS_BLOCK,\
+                               i_engine,i_port,i_devAddr,\
+                               i_commandCode,i_i2cMuxBusSelector,i_i2cMuxPath)
+
+    #define DEVICE_I2C_SMBUS_WORD(i_engine,i_port,i_devAddr,i_commandCode,\
+                                   i_i2cMuxBusSelector,i_i2cMuxPath )\
+        DeviceFW::I2C, I2C_SMBUS_RW_W_CMD_PARAMS(DeviceFW::I2C_SMBUS_WORD,\
+                               i_engine,i_port,i_devAddr,\
+                               i_commandCode,i_i2cMuxBusSelector,i_i2cMuxPath)
+
+    #define DEVICE_I2C_SMBUS_BYTE(i_engine, i_port,i_devAddr,i_commandCode,\
+                                   i_i2cMuxBusSelector,i_i2cMuxPath)\
+        DeviceFW::I2C, I2C_SMBUS_RW_W_CMD_PARAMS(DeviceFW::I2C_SMBUS_BYTE,\
+                               i_engine,i_port,i_devAddr,\
+                               i_commandCode,i_i2cMuxBusSelector,i_i2cMuxPath)
+    /**
+     *  @brief Construct the device addressing parameters for the I2C SMBUS
+     *      data transfer commands that lack a command parameter
+     *
+     *  @param[in] i_engine Which I2C master engine to use
+     *  @param[in] i_port Which port to use from the I2C master engine above
+     *  @param[in] i_devAddr The device address to communicate with on a given
+     *      engine/port.
+     *  @param[in] i_i2cMuxBusSelector The I2C MUX bus selector
+     *  @param[in] i_i2cMuxPath The I2C MUX entity path
+     */
+    #define DEVICE_I2C_SMBUS_SEND_OR_RECV(i_engine, i_port, i_devAddr,\
+                                   i_i2cMuxBusSelector,i_i2cMuxPath)\
+        DeviceFW::I2C, I2C_SMBUS_RW_WO_CMD_PARAMS(\
+                               DeviceFW::I2C_SMBUS_SEND_OR_RECV,\
+                               i_engine,i_port,i_devAddr,\
+                               i_i2cMuxBusSelector,i_i2cMuxPath)
+
+    /**
      * Construct the device addressing parameters for the I2C-offset device ops.
      * @param[in] i_port - Which port to use from the I2C master.
      * @param[in] i_engine - Which I2C master engine to use.
@@ -184,6 +273,7 @@ namespace DeviceFW
 #define DEVICE_I2C_CONTROL_PAGE_OP( i_port, i_engine, i_shouldLock,\
                                     i_desired_page, i_lockMutex )\
             DeviceFW::I2C,\
+            static_cast<uint64_t>(DeviceFW::I2C_PAGE_OP),\
             static_cast<uint64_t>(i_port),\
             static_cast<uint64_t>(i_engine),\
             0xffffffff,\
diff --git a/src/include/usr/hbotcompid.H b/src/include/usr/hbotcompid.H
index c9987ac6d..e3a3ec5d7 100644
--- a/src/include/usr/hbotcompid.H
+++ b/src/include/usr/hbotcompid.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2018                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2019                        */
 /* [+] Google Inc.                                                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
@@ -476,6 +476,15 @@ const char SMF_COMP_NAME[] = "smf";
 
 //@}
 
+/** @name UCD
+ *  UCD flash update component
+ */
+//@{
+const compId_t UCD_COMP_ID = 0x4100;
+const char UCD_COMP_NAME[] = "ucd";
+
+//@}
+//
 /** @name HDAT
  *  HDAT component
  *  @Note HDAT_COMP_ID=0x9000 matches with what
diff --git a/src/include/usr/i2c/i2creasoncodes.H b/src/include/usr/i2c/i2creasoncodes.H
index 6b08aefc2..6e29065db 100644
--- a/src/include/usr/i2c/i2creasoncodes.H
+++ b/src/include/usr/i2c/i2creasoncodes.H
@@ -77,30 +77,35 @@ enum i2cModuleId
  */
 enum i2cReasonCode
 {
-    I2C_INVALID_REASONCODE               = I2C_COMP_ID | 0x00,   // Invalid Reasoncode
-    I2C_INVALID_DATA_BUFFER              = I2C_COMP_ID | 0x01,   // Invalid Data Buffer pointer
-    I2C_INVALID_OP_TYPE                  = I2C_COMP_ID | 0x02,   // Invalid Operation type
-    I2C_FIFO_TIMEOUT                     = I2C_COMP_ID | 0x03,   // Timed out waiting on FIFO
-    I2C_BUS_NOT_READY                    = I2C_COMP_ID | 0x04,   // Bus Not ready
-    I2C_CMD_COMP_TIMEOUT                 = I2C_COMP_ID | 0x05,   // Timeout waiting for Cmd Complete
-    I2C_HW_ERROR_FOUND                   = I2C_COMP_ID | 0x06,   // Error found in status register
-    I2C_MASTER_SENTINEL_TARGET           = I2C_COMP_ID | 0x07,   // Master Sentinel used as target
-    I2C_NO_CENTAUR_FOUND                 = I2C_COMP_ID | 0x08,   // No Centaur chip found
-    I2C_NO_PROC_FOUND                    = I2C_COMP_ID | 0x09,   // No Processor chip found
-    I2C_ATTRIBUTE_NOT_FOUND              = I2C_COMP_ID | 0x0A,   // Needed I2C-related Attribute not found
-    I2C_NACK_ONLY_FOUND                  = I2C_COMP_ID | 0x0B,   // Only NACK found in status register
-    I2C_ARBITRATION_LOST_ONLY_FOUND      = I2C_COMP_ID | 0x0C,   // Bus Arbi lost found in status reg
-    I2C_RUNTIME_INTERFACE_ERR            = I2C_COMP_ID | 0x0D,   // Read/write unavailable at runtime
-    I2C_RUNTIME_ERR                      = I2C_COMP_ID | 0x0E,   // Failed run-time operation
-    I2C_RUNTIME_INVALID_OFFSET_LENGTH    = I2C_COMP_ID | 0x0F,   // Offset length of invalid size
-    I2C_INVALID_EEPROM_PAGE_MUTEX        = I2C_COMP_ID | 0x10,   // Error getting page mutex for i2c engine.
-    I2C_INVALID_EEPROM_PAGE_REQUEST      = I2C_COMP_ID | 0x11,   // Invalid EEPROM page request
-    I2C_FAILURE_UNLOCKING_EEPROM_PAGE    = I2C_COMP_ID | 0x12,   // Error while attempting to unlock the eeprom page
-    INVALID_MASTER_TARGET                = I2C_COMP_ID | 0x13,   // Master I2C target not valid
-    I2C_MUX_TARGET_NOT_FOUND             = I2C_COMP_ID | 0x14,   // The MUX target is not valid (null)
-    I2C_MUX_TARGET_NON_FUNCTIONAL        = I2C_COMP_ID | 0x15,   // The MUX target is non functional
-    I2C_INVALID_LENGTH                   = I2C_COMP_ID | 0x16,   // Invalid data buffer length passed to function
-    I2C_NULL_MASTER_TARGET               = I2C_COMP_ID | 0x17,   // Target Service's toPath() returned nullptr for target
+    I2C_INVALID_REASONCODE                = I2C_COMP_ID | 0x00,   // Invalid Reasoncode
+    I2C_INVALID_DATA_BUFFER               = I2C_COMP_ID | 0x01,   // Invalid Data Buffer pointer
+    I2C_INVALID_OP_TYPE                   = I2C_COMP_ID | 0x02,   // Invalid Operation type
+    I2C_FIFO_TIMEOUT                      = I2C_COMP_ID | 0x03,   // Timed out waiting on FIFO
+    I2C_BUS_NOT_READY                     = I2C_COMP_ID | 0x04,   // Bus Not ready
+    I2C_CMD_COMP_TIMEOUT                  = I2C_COMP_ID | 0x05,   // Timeout waiting for Cmd Complete
+    I2C_HW_ERROR_FOUND                    = I2C_COMP_ID | 0x06,   // Error found in status register
+    I2C_MASTER_SENTINEL_TARGET            = I2C_COMP_ID | 0x07,   // Master Sentinel used as target
+    I2C_NO_CENTAUR_FOUND                  = I2C_COMP_ID | 0x08,   // No Centaur chip found
+    I2C_NO_PROC_FOUND                     = I2C_COMP_ID | 0x09,   // No Processor chip found
+    I2C_ATTRIBUTE_NOT_FOUND               = I2C_COMP_ID | 0x0A,   // Needed I2C-related Attribute not found
+    I2C_NACK_ONLY_FOUND                   = I2C_COMP_ID | 0x0B,   // Only NACK found in status register
+    I2C_ARBITRATION_LOST_ONLY_FOUND       = I2C_COMP_ID | 0x0C,   // Bus Arbi lost found in status reg
+    I2C_RUNTIME_INTERFACE_ERR             = I2C_COMP_ID | 0x0D,   // Read/write unavailable at runtime
+    I2C_RUNTIME_ERR                       = I2C_COMP_ID | 0x0E,   // Failed run-time operation
+    I2C_RUNTIME_INVALID_OFFSET_LENGTH     = I2C_COMP_ID | 0x0F,   // Offset length of invalid size
+    I2C_INVALID_EEPROM_PAGE_MUTEX         = I2C_COMP_ID | 0x10,   // Error getting page mutex for i2c engine.
+    I2C_INVALID_EEPROM_PAGE_REQUEST       = I2C_COMP_ID | 0x11,   // Invalid EEPROM page request
+    I2C_FAILURE_UNLOCKING_EEPROM_PAGE     = I2C_COMP_ID | 0x12,   // Error while attempting to unlock the eeprom page
+    INVALID_MASTER_TARGET                 = I2C_COMP_ID | 0x13,   // Master I2C target not valid
+    I2C_MUX_TARGET_NOT_FOUND              = I2C_COMP_ID | 0x14,   // The MUX target is not valid (null)
+    I2C_MUX_TARGET_NON_FUNCTIONAL         = I2C_COMP_ID | 0x15,   // The MUX target is non functional
+    I2C_INVALID_LENGTH                    = I2C_COMP_ID | 0x16,   // Invalid data buffer length passed to function
+    I2C_NULL_MASTER_TARGET                = I2C_COMP_ID | 0x17,   // Target Service's toPath() returned nullptr for target
+    I2C_INVALID_SEND_BYTE_LENGTH          = I2C_COMP_ID | 0x18,   // Invalid send byte length
+    I2C_INVALID_WRITE_BYTE_OR_WORD_LENGTH = I2C_COMP_ID | 0x19,   // Invalid write byte/word length
+    I2C_INVALID_BLOCK_WRITE_LENGTH        = I2C_COMP_ID | 0x1A,   // Invalid block write length
+    I2C_INVALID_READ_BYTE_OR_WORD_LENGTH  = I2C_COMP_ID | 0x1B,   // Invalid read byte/word length
+    I2C_INVALID_BLOCK_READ_LENGTH         = I2C_COMP_ID | 0x1C,   // Invalid block read length
 };
 
 
diff --git a/src/include/usr/initservice/initsvcstructs.H b/src/include/usr/initservice/initsvcstructs.H
index b1d4723e1..1dfd11638 100644
--- a/src/include/usr/initservice/initsvcstructs.H
+++ b/src/include/usr/initservice/initsvcstructs.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2019                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -41,7 +41,7 @@
 #include <initservice/initsvcstructs.H>
 
 // This constant has a corresponding entry in src/build/tools/listdeps.pl.
-#define MAX_DEPENDENT_MODULES   10
+#define MAX_DEPENDENT_MODULES   12
 
 
 namespace   INITSERVICE
diff --git a/src/include/usr/isteps/istep21list.H b/src/include/usr/isteps/istep21list.H
index fabfc4be6..d9c3e5515 100644
--- a/src/include/usr/isteps/istep21list.H
+++ b/src/include/usr/isteps/istep21list.H
@@ -135,6 +135,9 @@ const DepModInfo  g_istep21Dependancies = {
 #ifdef CONFIG_NVDIMM
         DEP_LIB(libnvdimm.so),
 #endif
+#ifdef CONFIG_UCD_FLASH_UPDATES
+        DEP_LIB(libucd.so),
+#endif
         NULL
     }
 };
diff --git a/src/include/usr/isteps/ucd/updateUcdFlash.H b/src/include/usr/isteps/ucd/updateUcdFlash.H
new file mode 100644
index 000000000..a1487e78d
--- /dev/null
+++ b/src/include/usr/isteps/ucd/updateUcdFlash.H
@@ -0,0 +1,64 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/include/usr/isteps/ucd/updateUcdFlash.H $                 */
+/*                                                                        */
+/* OpenPOWER HostBoot Project                                             */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2019                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+#ifndef __UPDATE_UCD_FLASH_H
+#define __UPDATE_UCD_FLASH_H
+
+#include <targeting/common/target.H>
+#include <errl/errlentry.H>
+
+namespace POWER_SEQUENCER
+{
+
+namespace TI // Texas Instruments
+{
+
+namespace UCD // UCD series
+{
+
+/**
+ *  @brief Updates a UCD target's flash image
+ *
+ *  @param[in] i_pUcd UCD's target; must not be nullptr
+ *  @param[in] i_pFlashImage pointer to the start of the data flash
+ *      image (its table of contents).  Must not be nullptr.
+ *
+ *  @return errlHndl_t Error log handle
+ *  @retval nullptr Successfully updated the UCD's data flash image
+ *  @retval !nullptr Failed to update the UCD's data flash image.  Handle
+ *      points to valid error log
+ */
+errlHndl_t updateUcdFlash(
+          TARGETING::Target* i_pUcd,
+    const void*              i_pFlashImage);
+
+} // End namespace POWER_SEQUENCER
+
+} // End namespace TI
+
+} // End namespace UCD
+
+#endif // __UPDATE_UCD_FLASH_H
+