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| author | nagendra <nagendra.g@in.ibm.com> | 2015-07-24 13:55:08 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2015-10-15 15:00:13 -0500 |
| commit | 29bd2509664ce1040eb98797857d1dc76a0fa42f (patch) | |
| tree | 5bcd33f0f4add9361caf5cab92c16d03d91a2b16 /src/include/usr/vpd/spdenums.H | |
| parent | 568932e9e7a3f6b2e06ef7ec48fb10ed5d3e1f93 (diff) | |
| download | talos-hostboot-29bd2509664ce1040eb98797857d1dc76a0fa42f.tar.gz talos-hostboot-29bd2509664ce1040eb98797857d1dc76a0fa42f.zip | |
New SPD and VPD attributes support for DDR4 DIMM enablement
. Added new SPD attributes support as per DDR4 JEDEC
. Added new VPD attributes as per ver5 Membuff vpd
Change-Id: I9b3eabe6fe1c804b88429548fbac7adf08d8f6ae
RTC: 116143
CQ: SW325324
Backport: release-fips840
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19337
Tested-by: Jenkins Server
Tested-by: Jenkins OP Build CI
Tested-by: Jenkins OP HW
Tested-by: FSP CI Jenkins
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/include/usr/vpd/spdenums.H')
| -rw-r--r-- | src/include/usr/vpd/spdenums.H | 39 |
1 files changed, 35 insertions, 4 deletions
diff --git a/src/include/usr/vpd/spdenums.H b/src/include/usr/vpd/spdenums.H index d429690cf..b728e3fbf 100644 --- a/src/include/usr/vpd/spdenums.H +++ b/src/include/usr/vpd/spdenums.H @@ -163,7 +163,7 @@ enum LRMM_NUM_ROWS = SPD_FIRST_MOD_SPEC | 0x0e, LRMM_MIRRORING = SPD_FIRST_MOD_SPEC | 0x0f, LRMM_REVISION_NUM = SPD_FIRST_MOD_SPEC | 0x10, - LRMM_MFR_ID_CODE = SPD_FIRST_MOD_SPEC | 0x11, + MODSPEC_MM_MFR_ID_CODE = SPD_FIRST_MOD_SPEC | 0x11, // ============================================================== // Module Specific Keywords (Available for DDR3 DIMMs only) @@ -309,9 +309,31 @@ enum MODSPEC_COM_RAW_CARD_EXT = SPD_FIRST_MOD_SPEC | 0x9a, UMM_CRC = SPD_FIRST_MOD_SPEC | 0x9b, RMM_ADDR_MAPPING = SPD_FIRST_MOD_SPEC | 0x9c, - RMM_CRC = SPD_FIRST_MOD_SPEC | 0x9d, - LRMM_CRC = SPD_FIRST_MOD_SPEC | 0x9e, - SPD_LAST_MOD_SPEC = SPD_FIRST_MOD_SPEC | 0x9e, + MODSPEC_MM_ATTRIBS = SPD_FIRST_MOD_SPEC | 0x9d, + MODSPEC_MM_ADDR_MAPPING = SPD_FIRST_MOD_SPEC | 0x9e, + MODSPEC_MM_DRV_STRENGTH_CNTL = SPD_FIRST_MOD_SPEC | 0x9f, + MODSPEC_MM_DRV_STRENGTH_CK = SPD_FIRST_MOD_SPEC | 0xa0, + LRMM_VREF_DQ_RANK0 = SPD_FIRST_MOD_SPEC | 0xa1, + LRMM_VREF_DQ_RANK1 = SPD_FIRST_MOD_SPEC | 0xa2, + LRMM_VREF_DQ_RANK2 = SPD_FIRST_MOD_SPEC | 0xa3, + LRMM_VREF_DQ_RANK3 = SPD_FIRST_MOD_SPEC | 0xa4, + LRMM_VREF_DQ_FOR_DRAM = SPD_FIRST_MOD_SPEC | 0xa5, + LRMM_MDQ_DRV_LT_1866 = SPD_FIRST_MOD_SPEC | 0xa6, + LRMM_MDQ_DRV_1866_2400 = SPD_FIRST_MOD_SPEC | 0xa7, + LRMM_MDQ_DRV_2400_3200 = SPD_FIRST_MOD_SPEC | 0xa8, + LRMM_DRV_STRENGTH = SPD_FIRST_MOD_SPEC | 0xa9, + LRMM_ODT_RTT_WR_LT_1866 = SPD_FIRST_MOD_SPEC | 0xaa, + LRMM_ODT_RTT_NOM_LT_1866 = SPD_FIRST_MOD_SPEC | 0xab, + LRMM_ODT_RTT_WR_1866_2400 = SPD_FIRST_MOD_SPEC | 0xac, + LRMM_ODT_RTT_NOM_1866_2400 = SPD_FIRST_MOD_SPEC | 0xad, + LRMM_ODT_RTT_WR_2400_3200 = SPD_FIRST_MOD_SPEC | 0xae, + LRMM_ODT_RTT_NOM_2400_3200 = SPD_FIRST_MOD_SPEC | 0xaf, + LRMM_ODT_RTT_PARK_LT_1866 = SPD_FIRST_MOD_SPEC | 0xb0, + LRMM_ODT_RTT_PARK_1866_2400 = SPD_FIRST_MOD_SPEC | 0xb1, + LRMM_ODT_RTT_PARK_2400_3200 = SPD_FIRST_MOD_SPEC | 0xb2, + RMM_CRC = SPD_FIRST_MOD_SPEC | 0xb3, + LRMM_CRC = SPD_FIRST_MOD_SPEC | 0xb4, + SPD_LAST_MOD_SPEC = SPD_FIRST_MOD_SPEC | 0xb5, // This keyword should be last in the list // Invalid Keyword @@ -319,6 +341,15 @@ enum INVALID_SPD_KEYWORD = 0xFFFF, }; +enum +{ + // These are LRDIMM values for Module Type attribute + // according to ver3 and ver4 JEDEC specs + JEDEC_VER3_LRDIMM_VAL = 0x0b, + JEDEC_VER4_LRDIMM_VAL = 0x04, +}; + + }; // end SPD #endif |
