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author | Nick Bofferding <bofferdn@us.ibm.com> | 2018-05-31 01:04:19 -0500 |
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committer | William G. Hoffa <wghoffa@us.ibm.com> | 2018-06-04 15:58:42 -0400 |
commit | b81a9c8640e667af65e830fc35ce23db323f916a (patch) | |
tree | 9574d87cc50c08d7fc199e3153bb6cd3ae3d1a38 /src/include/usr/scom | |
parent | f9aa8f06bbd8250f63725080e189ce4719fd1253 (diff) | |
download | talos-hostboot-b81a9c8640e667af65e830fc35ce23db323f916a.tar.gz talos-hostboot-b81a9c8640e667af65e830fc35ce23db323f916a.zip |
Secure Boot: Defer init of Centaur SCOM cache register definitions
Defer init of Centaur SCOM cache register definitions until after istep 10.2
Change-Id: Ifdf94d00d65b0dffe841a32698f1aec5a97f3fe6
RTC: 187288
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59615
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
Reviewed-by: ILYA SMIRNOV <ismirno@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src/include/usr/scom')
-rw-r--r-- | src/include/usr/scom/centaurScomCache.H | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/include/usr/scom/centaurScomCache.H b/src/include/usr/scom/centaurScomCache.H index 013976384..94f345694 100644 --- a/src/include/usr/scom/centaurScomCache.H +++ b/src/include/usr/scom/centaurScomCache.H @@ -184,9 +184,10 @@ class ScomCache * @par Detailed Description: * Builds a SCOM register cache seeded with expected hardware * initialization values for each security sensitive register, and - * clones it to every Centaur + * clones it to every Centaur. Also instantiates the register + * definitions. */ - void init() const; + void init(); /** * @brief Globally enables caching of read/write SCOM requests for every @@ -210,9 +211,10 @@ class ScomCache bool cacheEnabled() const; /** - * @brief Delete all Centaurs' SCOM register cache + * @brief Delete all Centaurs' SCOM register cache and the + * global register definitions */ - void destroy() const; + void destroy(); /** * @brief If caching enabled and register is sensitive, writes the |