diff options
author | Tsung Yeung <tyeung@us.ibm.com> | 2018-12-20 10:39:39 -0600 |
---|---|---|
committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2019-02-12 10:50:42 -0600 |
commit | b2027cd8b704587be6ce4dd14327e6730f9d519b (patch) | |
tree | bf1b0206440c5105e46db51bb1a837ac71290ce9 /src/include/usr/isteps | |
parent | 95bbfc78a463c06cd06204ee8cb1b904ec864565 (diff) | |
download | talos-hostboot-b2027cd8b704587be6ce4dd14327e6730f9d519b.tar.gz talos-hostboot-b2027cd8b704587be6ce4dd14327e6730f9d519b.zip |
Disable NVDIMM Trigger Before Draminit and Deassert DDR_RESETn During MPIPL
- Per the JEDEC spec, DDR_RESETn is masked from the DRAM when the NVDIMM
is armed. This could cause the training to fail if the trigger is not
disabled before training. Two scenarios where this can happen are warm
reboot and cold boot before the backup power module can deplete the
charge
- Deassert DDR_RESETn in MPIPL before triggering the restore.
- Fix the config flag to enable NVDIMM code
Change-Id: I9d25c2f653fc54d379f0dbab49218f5b59a407a0
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70035
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/include/usr/isteps')
-rw-r--r-- | src/include/usr/isteps/istep13list.H | 5 | ||||
-rw-r--r-- | src/include/usr/isteps/istep14list.H | 6 | ||||
-rw-r--r-- | src/include/usr/isteps/istep21list.H | 5 | ||||
-rw-r--r-- | src/include/usr/isteps/nvdimm/nvdimm.H | 20 |
4 files changed, 27 insertions, 9 deletions
diff --git a/src/include/usr/isteps/istep13list.H b/src/include/usr/isteps/istep13list.H index fd0430c6c..d4788913d 100644 --- a/src/include/usr/isteps/istep13list.H +++ b/src/include/usr/isteps/istep13list.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2017 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] Google Inc. */ /* [+] International Business Machines Corp. */ /* */ @@ -296,6 +296,9 @@ const DepModInfo g_istep13Dependancies = { DEP_LIB(libistep13.so), DEP_LIB(libisteps_mss.so), DEP_LIB(libcen.so), +#ifdef CONFIG_NVDIMM + DEP_LIB(libnvdimm.so), +#endif NULL } }; diff --git a/src/include/usr/isteps/istep14list.H b/src/include/usr/isteps/istep14list.H index 1a2058167..bf5b00453 100644 --- a/src/include/usr/isteps/istep14list.H +++ b/src/include/usr/isteps/istep14list.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2018 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -169,7 +169,11 @@ namespace INITSERVICE { ISTEPNAME(14,04,"mss_power_cleanup"), ISTEP_14::call_mss_power_cleanup, +#ifdef CONFIG_NVDIMM + { START_FN, EXT_IMAGE, MPIPL_OP | NORMAL_IPL_OP, true } +#else { START_FN, EXT_IMAGE, NORMAL_IPL_OP, true } +#endif }, { ISTEPNAME(14,05,"proc_setup_bars"), diff --git a/src/include/usr/isteps/istep21list.H b/src/include/usr/isteps/istep21list.H index 582ecf292..fabfc4be6 100644 --- a/src/include/usr/isteps/istep21list.H +++ b/src/include/usr/isteps/istep21list.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2018 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] Google Inc. */ /* [+] International Business Machines Corp. */ /* */ @@ -132,6 +132,9 @@ const DepModInfo g_istep21Dependancies = { #ifndef CONFIG_FSP_BUILD DEP_LIB(libnvram.so), #endif +#ifdef CONFIG_NVDIMM + DEP_LIB(libnvdimm.so), +#endif NULL } }; diff --git a/src/include/usr/isteps/nvdimm/nvdimm.H b/src/include/usr/isteps/nvdimm/nvdimm.H index c1df3033e..6f6b46541 100644 --- a/src/include/usr/isteps/nvdimm/nvdimm.H +++ b/src/include/usr/isteps/nvdimm/nvdimm.H @@ -29,7 +29,7 @@ namespace NVDIMM { -enum +enum nvdimm_err_status { NSTD_VAL_NOPRSV = 0x08, // memory valid, contents not preserved (genesis) NSTD_VAL_NOPRSV_MASK = 0xF7, @@ -41,6 +41,7 @@ enum NSTD_ERR_NOBKUP_MASK = 0xFE, NSTD_ERR = 0x03, // NSTD_ERR_NOPRSV+NSTD_ERR_NOBKUP }; + #ifndef __HOSTBOOT_RUNTIME /** * @brief Entry function to NVDIMM management @@ -76,7 +77,6 @@ errlHndl_t nvdimmEraseNF(TARGETING::Target *i_nvdimm); */ void nvdimmSetStatusFlag(TARGETING::Target *i_nvdimm, const uint8_t i_status_flag); - #ifdef __HOSTBOOT_RUNTIME /** @@ -89,15 +89,16 @@ void nvdimmSetStatusFlag(TARGETING::Target *i_nvdimm, const uint8_t i_status_fla bool nvdimmInErrorState(TARGETING::Target *i_nvdimm); /** - * @brief This function arms the trigger to enable backup in the event - * of power loss (DDR Reset_n goes low) + * @brief This function arms/disarms the trigger based on i_state * * @param[in] i_nvdimm - nvdimm target with NV controller * + * @param[in] i_state - true to arm, false to disarm + * * @return errlHndl_t - Null if successful, otherwise a pointer to * the error log. */ -errlHndl_t nvdimmArmResetN(TARGETING::Target *i_nvdimm); +errlHndl_t nvdimmChangeArmState(TARGETING::Target *i_nvdimm, bool i_state); /** * @brief Arms the trigger to enable backup in the event of a power loss @@ -113,7 +114,6 @@ errlHndl_t nvdimmArmResetN(TARGETING::Target *i_nvdimm); */ bool nvdimmArm(TARGETING::TargetHandleList &i_nvdimmTargetList); - /** * @brief NVDIMM protection state * @@ -139,6 +139,14 @@ enum nvdimm_protection_t errlHndl_t notifyNvdimmProtectionChange(TARGETING::Target* i_target, const nvdimm_protection_t i_state); #endif +/** + * @brief Entry function to NVDIMM initialization + * - Checks for ready state + * - Waits for the ongoing backup to complete + * - Disarms the trigger for draminit + * @param i_target nvdimm target + */ +void nvdimm_init(TARGETING::Target *i_nvdimm); } |