IPL Time Checkstop Analysis Part 1: Load OCC

First part of the IPL Time Checkstop Analysis story.
The OCC image gets loaded from the PNOR directly into
SRAM in istep 6.11. The OCC is reset in step 21.1
and the image is reloaded to HOMER.

Change-Id: I73ce96b81b311d7ae54356c64aeec816d52fafbb
RTC:155065
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43574
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

1 files changed, 25 insertions, 7 deletions

diff --git a/src/include/usr/isteps/pm/occCheckstop.H b/src/include/usr/isteps/pm/occCheckstop.H
index 4fa55bfd4..10efd4897 100644
--- a/src/include/usr/isteps/pm/occCheckstop.H
+++ b/src/include/usr/isteps/pm/occCheckstop.H
@@ -47,17 +47,21 @@ namespace HBOCC
         NOT_FIR_MASTER = 0x00000000,
         IS_FIR_MASTER  = 0x00000001,
 
-        // SRAM Address for OCC Main App
-        OCC_SRAM_ADDRESS = 0xFFF80000,
+        // SRAM Addresses for OCC Main App and GPE0 app
+        OCC_405_SRAM_ADDRESS  = 0xFFF40000,
+        OCC_GPE0_SRAM_ADDRESS = 0xFFF01000,
+        OCC_GPE1_SRAM_ADDRESS = 0xFFF10000,
 
         // SRAM Address and length for FIR HOMER data
-        OCC_SRAM_FIR_DATA   = 0xFFFF5000,
-        OCC_SRAM_FIR_LENGTH = 0x1000,
+        OCC_SRAM_FIR_DATA   = 0xFFFBA000,
+        OCC_SRAM_FIR_LENGTH = 0x3000,
 
         // offsets for OCC loading during IPL
-        OCC_OFFSET_LENGTH   = 0x48,
-        OCC_OFFSET_IPL_FLAG = 0x82,
-        OCC_OFFSET_FREQ     = 0x84,
+        OCC_OFFSET_LENGTH      = 0x48,
+        OCC_OFFSET_GPE0_LENGTH = 0x64,
+        OCC_OFFSET_GPE1_LENGTH = 0x68,
+        OCC_OFFSET_IPL_FLAG    = 0x92,
+        OCC_OFFSET_FREQ        = 0x94,
 
     };
 
@@ -92,6 +96,20 @@ namespace HBOCC
                     const PRDF::HwInitialized_t i_curHw = PRDF::ALL_HARDWARE);
 #endif
 
+#ifdef CONFIG_IPLTIME_CHECKSTOP_ANALYSIS
+    /**
+     * @brief Loads the OCC image from PNOR to SRAM
+     *
+     * @param[in] i_target: the proc we're operating on (should be masterproc)
+     * @param[in] i_occVirtAddr: the address of the page allocated for OCC
+     *                           bootloader.
+     *
+     * @return errlHndl_t Error log if load fails
+     */
+    errlHndl_t loadOCCImageDuringIpl(TARGETING::Target* i_target,
+                                      void* i_occVirtAddr);
+#endif
+
     /**
      * @brief Execute procedures and steps required to load
      *        OCC data in a specified processor