Clean up OCC and enable HTMGT

Change-Id: I0903f4bd504589d4d5931b4b3b6206664f39b119
RTC:171441
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39736
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sheldon R. Bailey <baileysh@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

3 files changed, 254 insertions, 0 deletions

diff --git a/src/include/usr/isteps/pm/occAccess.H b/src/include/usr/isteps/pm/occAccess.H
new file mode 100644
index 000000000..a5b46ff45
--- /dev/null
+++ b/src/include/usr/isteps/pm/occAccess.H
@@ -0,0 +1,74 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/include/usr/isteps/pm/occAccess.H $                       */
+/*                                                                        */
+/* OpenPOWER HostBoot Project                                             */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2017                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef OCCACCESS_H_
+#define OCCACCESS_H_
+
+#include <config.h>
+#include <errl/errlentry.H>
+#include <targeting/common/commontargeting.H>
+
+namespace HBOCC
+{
+    /**
+     * @brief Read OCC SRAM
+     *
+     * @param[in]     i_pTarget   PROC or OCC target pointer
+     * @param[in]     i_addr      OCI Address to be used for the operation
+     * @param[in,out] io_dataBuf  Reference to data buffer
+     * @param[in]     i_dataLen   Size of the data to read
+     * @return errlHndl_t   Error log if operation failed
+     */
+    errlHndl_t readSRAM(const TARGETING::Target*i_pTarget,
+                        const uint32_t i_addr,
+                        uint64_t * io_dataBuf,
+                        size_t i_dataLen );
+
+    /**
+     * @brief Write OCC SRAM
+     *
+     * @param[in]     i_pTarget   PROC or OCC target pointer
+     * @param[in]     i_addr      OCI Address to be used for the operation
+     * @param[in]     i_dataBuf   Reference to data buffer
+     * @param[in]     i_dataLen   Size of the data to write
+     * @return errlHndl_t   Error log if operation failed
+     */
+    errlHndl_t writeSRAM(const TARGETING::Target*i_pTarget,
+                         const uint32_t i_addr,
+                         uint64_t * io_dataBuf,
+                         size_t i_dataLen );
+
+    /**
+     * @brief Write OCC Circular Buffer
+     *
+     * @param[in]     i_pTarget   PROC or OCC target pointer
+     * @param[in]     i_dataBuf   Reference to data buffer
+     * @return errlHndl_t   Error log if operation failed
+     */
+    errlHndl_t writeCircularBuffer(const TARGETING::Target*i_pTarget,
+                                   uint64_t * i_dataBuf);
+
+} //end OCC namespace
+
+#endif
diff --git a/src/include/usr/isteps/pm/occCheckstop.H b/src/include/usr/isteps/pm/occCheckstop.H
new file mode 100644
index 000000000..6a13146cd
--- /dev/null
+++ b/src/include/usr/isteps/pm/occCheckstop.H
@@ -0,0 +1,155 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/include/usr/isteps/pm/occCheckstop.H $                    */
+/*                                                                        */
+/* OpenPOWER HostBoot Project                                             */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2017                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef OCC_CHECKSTOP_H
+#define OCC_CHECKSTOP_H
+
+#include <limits.h>
+#include <errl/errlentry.H>
+#include <diag/prdf/prdfWriteHomerFirData.H>
+
+namespace HBOCC
+{
+    enum
+    {
+        OccHostDataVersion = 3,
+        PRE_FIR_MASTER_VERSION = 2,
+
+        OCC_LIDID = 0x81e00430,
+        OCC_IBSCOM_RANGE_IN_MB = MEGABYTE,
+
+        // Interrupt Types
+        USE_FSI2HOST_MAILBOX = 0x00000000,
+        USE_PSIHB_COMPLEX    = 0x00000001,
+
+        // FIR Master
+        NOT_FIR_MASTER = 0x00000000,
+        IS_FIR_MASTER  = 0x00000001,
+
+        // SRAM Address for OCC Main App
+        OCC_SRAM_ADDRESS = 0xFFF80000,
+
+        // SRAM Address and length for FIR HOMER data
+        OCC_SRAM_FIR_DATA   = 0xFFFF5000,
+        OCC_SRAM_FIR_LENGTH = 0x1000,
+
+        // offsets for OCC loading during IPL
+        OCC_OFFSET_LENGTH   = 0x48,
+        OCC_OFFSET_IPL_FLAG = 0x82,
+        OCC_OFFSET_FREQ     = 0x84,
+
+    };
+
+    enum occAction_t
+    {
+        OCC_START,
+        OCC_STOP,
+    };
+    /**
+     * @brief Sets up OCC Host data in Homer
+     *
+     * @param[in] i_proc:         target processor to load
+     * @param[in] i_occHostDataVirtAddr Virtual
+     *                       address of current
+     *                       proc's Host data area.
+     *
+     * @return errlHndl_t  Error log Host data setup failed
+     */
+    errlHndl_t loadHostDataToHomer(TARGETING::Target* i_proc,
+                                   void* i_occHostDataVirtAddr);
+
+#ifdef CONFIG_IPLTIME_CHECKSTOP_ANALYSIS
+    /**
+     * @brief Sets up OCC Host data in SRAM
+     *
+     * @param[in] i_proc:   target processor to load
+     * @param[in] i_curHW:  enum indicating which HW is currently known
+     *
+     * @return errlHndl_t   Error log Host data setup failed
+     */
+    errlHndl_t loadHostDataToSRAM(TARGETING::Target* i_proc,
+                    const PRDF::HwInitialized_t i_curHw = PRDF::ALL_HARDWARE);
+#endif
+
+    /**
+     * @brief Execute procedures and steps required to load
+     *        OCC data in a specified processor
+     *
+     * @param[in] i_target:         Target processor
+     * @param[in] i_occImgPaddr:    Physical address of current
+     *                                 proc's OCC image in the homer
+     * @param[in] i_occImgVaddr:  Virtual address of current
+     *                                 proc's OCC image int the homer
+     * @param[in] i_commonPhysAddr: Physical address of common
+     *                              OCC region
+     * @param[in] i_useSRAM: bool - use SRAM for OCC image, ie during IPL
+     *     true if duringIPL, false if at end of IPL (default)
+     * @return errlHndl_t  Error log if loadOCC failed
+     */
+    errlHndl_t loadOCC(TARGETING::Target* i_target,
+                       uint64_t i_occImgPaddr,
+                       uint64_t i_occImgVaddr,
+                       uint64_t i_commonPhysAddr,
+                       bool i_useSRAM = false);
+
+    /**
+     * @brief Start OCC for specified DCM pair of processors.
+     *        If 2nd input is NULL, OCC will be setup on just
+     *        one target.
+     *
+     * @param[in] i_target0:    target of first processor in DCM pair
+     * @param[in] i_target1:    target of second processor in DCM pair
+     * @param[out] o_failedTarget failed target in case of an error
+     *
+     * @return errlHndl_t  Error log of startOCC failed
+     */
+    errlHndl_t startOCC (TARGETING::Target* i_target0,
+                         TARGETING::Target* i_target1,
+                         TARGETING::Target *& o_failedTarget);
+    /**
+     * @brief Stop OCC for specified DCM pair of processors.
+     *        If 2nd input is NULL, OCC will be setup on just
+     *        one target.
+     *
+     * @param[in] i_target0:    target of first processor in DCM pair
+     * @param[in] i_target1:    target of second processor in DCM pair
+     *
+     * @return errlHndl_t  Error log of stopOCC failed
+     */
+    errlHndl_t stopOCC(TARGETING::Target * i_target0,
+                       TARGETING::Target * i_target1);
+
+    /**
+     * @brief Stops OCCs on all Processors in the node
+     *        Function will attempt to stop all OCCs and commit
+     *        logs inline.  An error will only be returned for
+     *        very unexpected software fails.
+     *
+     * @return errlHndl_t  Error log if OCC load failed
+     */
+    errlHndl_t stopAllOCCs();
+
+} //namespace HBOCC ends
+
+#endif // OCC_CHECKSTOP_H
diff --git a/src/include/usr/isteps/pm/pm_common_ext.H b/src/include/usr/isteps/pm/pm_common_ext.H
index a8428b73f..9a58c59ef 100644
--- a/src/include/usr/isteps/pm/pm_common_ext.H
+++ b/src/include/usr/isteps/pm/pm_common_ext.H
@@ -30,6 +30,31 @@
 namespace HBPM
 {
     /**
+     * @brief Host config data consumed by OCC
+     */
+    struct occHostConfigDataArea_t
+    {
+        uint32_t version;
+
+        //For computation of timebase frequency
+        uint32_t nestFrequency;
+
+        // For determining the interrupt type to Host
+        //  0x00000000 = Use FSI2HOST Mailbox
+        //  0x00000001 = Use OCC interrupt line through PSIHB complex
+        uint32_t interruptType;
+
+        // For informing OCC if it is the FIR master:
+        //  0x00000000 = Default
+        //  0x00000001 = FIR Master
+        uint32_t firMaster;
+
+        // FIR collection configuration data needed by FIR Master
+        //  OCC in the event of a checkstop
+        uint8_t firdataConfig[3072];
+    };
+
+    /**
      * @brief Enumeration of the load PM complex mode
      *      LOAD
      *       - Call pm_reset first