Move FSP-only attributes to common targeting for Open Power

- Added default lane masks to Hostboot system XML files
- Added PCIE config related module IDs and reason codes
- Added new packing function to combine 4x uint8 into 1x uint32
- Added dynamic PCIE config for SP-less environments
- Moved PCIE attributes into common attribute definition
- Attached new PCIE attributes to common target definition
- Defaulted PCIE lanes per proc appropriately for all proc chips
- Added CDM_DOMAIN attribute into common attribute definition
- Attached + defaulted CDM domain in common target definition
- Updated common MRW parser to customize the new PCIE attributes

Change-Id: I3779ca6e6a4803d7e78e21e47a92e0b1a09e657d
RTC: 113488
CMVC-coreq: 942076
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/13997
Tested-by: Jenkins Server
Reviewed-by: STEPHEN M. CPREK <smcprek@us.ibm.com>
Reviewed-by: Andrew J. Geissler <andrewg@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

1 files changed, 5 insertions, 0 deletions

diff --git a/src/include/usr/errl/hberrltypes.H b/src/include/usr/errl/hberrltypes.H
index 94e3722a8..e948e4df0 100644
--- a/src/include/usr/errl/hberrltypes.H
+++ b/src/include/usr/errl/hberrltypes.H
@@ -79,6 +79,11 @@ namespace ERRORLOG { class ErrlEntry; };
         ( (TO_UINT64(TWO_UINT16_TO_UINT32(mostleft_16, left_16)) << 32) | \
           (TO_UINT64(TWO_UINT16_TO_UINT32(right_16, mostright_16))) )
 
+// uint32_t val = 8bit:8bit:8bit:8bit
+#define FOUR_UINT8_TO_UINT32(mostleft_8, left_8, right_8, mostright_8) \
+        ( (TO_UINT32(TWO_UINT8_TO_UINT16(mostleft_8, left_8)) << 16) | \
+          (TO_UINT32(TWO_UINT8_TO_UINT16(right_8, mostright_8))) )
+
 namespace ERRORLOG
 {