diff options
| author | Dean Sanner <dsanner@us.ibm.com> | 2013-03-20 13:03:13 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2013-03-26 13:11:09 -0500 |
| commit | 94f86ee572bac366d912b2a01bab6c0ae851f4f3 (patch) | |
| tree | afe692d4e9d32d2f408a61ac98718018dcceb5c0 /src/include/kernel/intmsghandler.H | |
| parent | 88d3d790071151a03e71024c0a83d9dc75aa58b7 (diff) | |
| download | talos-hostboot-94f86ee572bac366d912b2a01bab6c0ae851f4f3.tar.gz talos-hostboot-94f86ee572bac366d912b2a01bab6c0ae851f4f3.zip | |
Changes required for A bus and 4 dimm support
Change-Id: I1670913709df9acd5cddf19feaccab6462125e5f
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3655
Tested-by: Jenkins Server
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/include/kernel/intmsghandler.H')
| -rw-r--r-- | src/include/kernel/intmsghandler.H | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/src/include/kernel/intmsghandler.H b/src/include/kernel/intmsghandler.H index b4042c950..73fbd9313 100644 --- a/src/include/kernel/intmsghandler.H +++ b/src/include/kernel/intmsghandler.H @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2011,2012 */ +/* COPYRIGHT International Business Machines Corp. 2011,2013 */ /* */ /* p1 */ /* */ @@ -63,7 +63,7 @@ class InterruptMsgHdlr : public MessageHandler P8_IP_THREADID_LSL = (12-0), P8_IP_COREID_LSL = (15-3), P8_IP_CHIPID_LSL = (20-7), - P8_IP_NODEID_LSL = (23-10), + P8_IP_NODEID_LSL = (22-10), XIRR_ADDR_OFFSET = 4, }; @@ -102,11 +102,13 @@ class InterruptMsgHdlr : public MessageHandler { uint64_t offset = 0; - // The node and chip id fields are adjacent in both the PIR and - // the mmio offset - so they can be done in one shift operation + // The PIR chip id field has 1 extra bit (8 chips), so we need + // to shift the node and chip separately offset |= - (i_pir & (P8_PIR_NODEID_MSK | P8_PIR_CHIPID_MSK)) - << P8_IP_CHIPID_LSL; + (i_pir & P8_PIR_NODEID_MSK) << P8_IP_NODEID_LSL; + + offset |= + (i_pir & P8_PIR_CHIPID_MSK) << P8_IP_CHIPID_LSL; // The core and thread id field are adjacent in both the PIR and // the mmio offset, so they can be done in one shift operation. |
