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| author | crgeddes <crgeddes@us.ibm.com> | 2017-05-22 16:59:28 -0500 |
|---|---|---|
| committer | William G. Hoffa <wghoffa@us.ibm.com> | 2017-06-02 12:12:11 -0400 |
| commit | f3dd0b07a4c57d2d7bb7fe1fda734c5caa69cf2e (patch) | |
| tree | 08919e88154cd39b16486f43c929642b672e6d55 /src/include/arch | |
| parent | f7f718f567895dc5e85747ad33e26ce07c4da4df (diff) | |
| download | talos-hostboot-f3dd0b07a4c57d2d7bb7fe1fda734c5caa69cf2e.tar.gz talos-hostboot-f3dd0b07a4c57d2d7bb7fe1fda734c5caa69cf2e.zip | |
Setup INTP bars correctly when memory is swapped on master proc
In the event that no memory is detected behind proc0. We will attempt
to use the memory behind a slave proc instead. When this occurs we
must adjust the interrupt bars to account for this swap
Change-Id: Ib37a190b7a7a2c655440ffd2bad56c351b4d4fa2
RTC: 173527
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40820
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Diffstat (limited to 'src/include/arch')
| -rw-r--r-- | src/include/arch/memorymap.H | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/include/arch/memorymap.H b/src/include/arch/memorymap.H index f102395fb..b20e43425 100644 --- a/src/include/arch/memorymap.H +++ b/src/include/arch/memorymap.H @@ -56,6 +56,11 @@ inline uint64_t computeMemoryMapOffset( uint64_t i_baseAddr, */ constexpr uint64_t MMIO_GROUP0_CHIP0_XSCOM_BASE_ADDR = 0x000603FC00000000; constexpr uint64_t MMIO_GROUP0_CHIP0_LPC_BASE_ADDR = 0x0006030000000000; +constexpr uint64_t MMIO_GROUP0_CHIP0_PSI_BRIDGE_BASE_ADDR = 0x0006030203000000; +constexpr uint64_t MMIO_GROUP0_CHIP0_XIVE_CONTROLLER_BASE_ADDR = 0x0006030203100000; +constexpr uint64_t MMIO_GROUP0_CHIP0_XIVE_THREAD_MGMT1_BASE_ADDR = 0x0006020000000000; +constexpr uint64_t MMIO_GROUP0_CHIP0_PSI_HB_ESB_BASE_ADDR = 0x00060302031C0000; +constexpr uint64_t MMIO_GROUP0_CHIP0_INTP_BASE_ADDR = 0x0003FFFF80000000; #endif //#ifndef _MEMORYMAP_H |
