From f3dd0b07a4c57d2d7bb7fe1fda734c5caa69cf2e Mon Sep 17 00:00:00 2001 From: crgeddes Date: Mon, 22 May 2017 16:59:28 -0500 Subject: Setup INTP bars correctly when memory is swapped on master proc In the event that no memory is detected behind proc0. We will attempt to use the memory behind a slave proc instead. When this occurs we must adjust the interrupt bars to account for this swap Change-Id: Ib37a190b7a7a2c655440ffd2bad56c351b4d4fa2 RTC: 173527 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40820 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Reviewed-by: Martin Gloff Reviewed-by: Daniel M. Crowell Reviewed-by: William G. Hoffa --- src/include/arch/memorymap.H | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/include/arch') diff --git a/src/include/arch/memorymap.H b/src/include/arch/memorymap.H index f102395fb..b20e43425 100644 --- a/src/include/arch/memorymap.H +++ b/src/include/arch/memorymap.H @@ -56,6 +56,11 @@ inline uint64_t computeMemoryMapOffset( uint64_t i_baseAddr, */ constexpr uint64_t MMIO_GROUP0_CHIP0_XSCOM_BASE_ADDR = 0x000603FC00000000; constexpr uint64_t MMIO_GROUP0_CHIP0_LPC_BASE_ADDR = 0x0006030000000000; +constexpr uint64_t MMIO_GROUP0_CHIP0_PSI_BRIDGE_BASE_ADDR = 0x0006030203000000; +constexpr uint64_t MMIO_GROUP0_CHIP0_XIVE_CONTROLLER_BASE_ADDR = 0x0006030203100000; +constexpr uint64_t MMIO_GROUP0_CHIP0_XIVE_THREAD_MGMT1_BASE_ADDR = 0x0006020000000000; +constexpr uint64_t MMIO_GROUP0_CHIP0_PSI_HB_ESB_BASE_ADDR = 0x00060302031C0000; +constexpr uint64_t MMIO_GROUP0_CHIP0_INTP_BASE_ADDR = 0x0003FFFF80000000; #endif //#ifndef _MEMORYMAP_H -- cgit v1.2.3