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| author | Ben Gass <bgass@us.ibm.com> | 2019-03-06 17:25:00 -0500 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2019-03-20 09:37:04 -0500 |
| commit | d27c5e1fe4313a349fa16a557299c6d0721cdbce (patch) | |
| tree | f2882ab00c4cdfca131efc34f1dc756228e2fbcb /src/import | |
| parent | e5a493e300da10cd6fe39ecb2e614d63dd11b9fb (diff) | |
| download | talos-hostboot-d27c5e1fe4313a349fa16a557299c6d0721cdbce.tar.gz talos-hostboot-d27c5e1fe4313a349fa16a557299c6d0721cdbce.zip | |
Update ATRMISS registers for Axone
The address changed and there are now two.
Change-Id: Iad60f8ec843ed61d28ef11903d8258ecfe213aa3
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72965
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72986
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/nest/p9_npu_scominit.C | 45 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml | 17 |
2 files changed, 51 insertions, 11 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_npu_scominit.C b/src/import/chips/p9/procedures/hwp/nest/p9_npu_scominit.C index b82040e89..cf3edc4f4 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_npu_scominit.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_npu_scominit.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -40,6 +40,8 @@ #include <p9_nv_ref_clk_enable.H> #include <p9_misc_scom_addresses.H> #include <p9_misc_scom_addresses_fld.H> +#include <p9a_misc_scom_addresses.H> +#include <p9a_misc_scom_addresses_fld.H> //------------------------------------------------------------------------------ // Constant definitions @@ -70,6 +72,7 @@ fapi2::ReturnCode p9_npu_scominit( fapi2::ReturnCode l_rc; fapi2::buffer<uint64_t> l_atrmiss = 0; fapi2::ATTR_CHIP_EC_FEATURE_SETUP_BARS_NPU_DD1_ADDR_Type l_npu_p9n_dd1; + fapi2::ATTR_CHIP_EC_FEATURE_SETUP_BARS_NPU_AXONE_ADDR_Type l_axone; // read attribute to determine if P9N DD1 NPU addresses should be used FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_SETUP_BARS_NPU_DD1_ADDR, @@ -77,6 +80,11 @@ fapi2::ReturnCode p9_npu_scominit( l_npu_p9n_dd1), "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_SETUP_BARS_NPU_DD1_ADDR)"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_SETUP_BARS_NPU_AXONE_ADDR, + i_target, + l_axone), + "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_SETUP_BARS_NPU_AXONE_ADDR)"); + // apply NPU SCOM inits from initfile FAPI_DBG("Invoking p9.npu.scom.initfile..."); FAPI_EXEC_HWP(l_rc, @@ -95,16 +103,31 @@ fapi2::ReturnCode p9_npu_scominit( l_atrmiss.setBit<PU_NPU_SM2_XTS_ATRMISS_FLAG_MAP>() .setBit<PU_NPU_SM2_XTS_ATRMISS_ENA>(); - FAPI_TRY(fapi2::putScomUnderMask(i_target, - ((l_npu_p9n_dd1) ? - (PU_NPU_SM2_XTS_ATRMISS) : - (PU_NPU_SM2_XTS_ATRMISS_POST_P9NDD1)), - l_atrmiss, - l_atrmiss), - "Error from putScomUnderMask (0x%08X)", - ((l_npu_p9n_dd1) ? - (PU_NPU_SM2_XTS_ATRMISS) : - (PU_NPU_SM2_XTS_ATRMISS_POST_P9NDD1))); + if (!l_axone) + { + FAPI_TRY(fapi2::putScomUnderMask(i_target, + ((l_npu_p9n_dd1) ? + (PU_NPU_SM2_XTS_ATRMISS) : + (PU_NPU_SM2_XTS_ATRMISS_POST_P9NDD1)), + l_atrmiss, + l_atrmiss), + "Error from putScomUnderMask (0x%08X)", + ((l_npu_p9n_dd1) ? + (PU_NPU_SM2_XTS_ATRMISS) : + (PU_NPU_SM2_XTS_ATRMISS_POST_P9NDD1))); + } + else + { + // Axone + // P9A_PU_NPU2_NTL1_XTS_ATRMISS = 0x050112FA + FAPI_TRY(fapi2::putScomUnderMask(i_target, P9A_PU_NPU2_NTL1_XTS_ATRMISS, l_atrmiss, l_atrmiss), + "Error from putScomUnderMask (0x%08X)", + P9A_PU_NPU2_NTL1_XTS_ATRMISS); + // P9A__NTL1_XTS_ATRMISS = 0x050116FA + FAPI_TRY(fapi2::putScomUnderMask(i_target, P9A__NTL1_XTS_ATRMISS, l_atrmiss, l_atrmiss), + "Error from putScomUnderMask (0x%08X)", + P9A__NTL1_XTS_ATRMISS); + } // enable NVLINK refclocks FAPI_DBG("Invoking p9_nv_ref_clk_enable..."); diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index 1e2d0ba75..9e797bfdf 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -6503,6 +6503,23 @@ </chip> </chipEcFeature> </attribute> + <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_SETUP_BARS_NPU_AXONE_ADDR</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Axone only: Use the Axone register addresses for the PHY0 BAR registers, PHY1 BAR registers, and MMIO BAR registers + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_AXONE</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> <!-- ********************************************************************* --> <attribute> <id>ATTR_CHIP_EC_FEATURE_SKEWADJ_P9NDD1_INIT</id> |
