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author | Brian Silver <bsilver@us.ibm.com> | 2016-08-24 08:25:02 -0500 |
---|---|---|
committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-08-24 23:46:40 -0400 |
commit | c24a75f24ea93874a66c5ad36dbf55cc1621ec5a (patch) | |
tree | 9a2bfcb05f36bc36469017b394a322f71e8a8986 /src/import | |
parent | e6059f6594051106f13391d2967ef7f37aa4ec29 (diff) | |
download | talos-hostboot-c24a75f24ea93874a66c5ad36dbf55cc1621ec5a.tar.gz talos-hostboot-c24a75f24ea93874a66c5ad36dbf55cc1621ec5a.zip |
Add informational error log for PHY during training
Change-Id: Ieb9115d2adeb73f732d73562d9ed26dd0f825149
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28720
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28724
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import')
-rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C | 15 | ||||
-rw-r--r-- | src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit_training.xml | 35 |
2 files changed, 47 insertions, 3 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C index f6672e434..85599f518 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C @@ -396,6 +396,19 @@ fapi2::ReturnCode process_initial_cal_errors( const fapi2::Target<TARGET_TYPE_MC fapi2::Target<TARGET_TYPE_DIMM> l_failed_dimm; + // Check the PC error status. If it's !0, we'll log an informational message + // which records the states of the individual PHY block error registers (this is + // in the collect register section in the XML) + FAPI_TRY( pc::read_error_status0(i_target, l_err_data) ); + + if (l_err_data != 0) + { + FAPI_ERR("seeing %s pc error_status0 0x%016lx", mss::c_str(i_target), l_err_data); + fapi2::MSS_DRAMINIT_PC_ERROR_INFO() + .set_PC_ERROR0(l_err_data) + .set_TARGET_IN_ERROR(i_target).execute(fapi2::FAPI2_ERRL_SEV_RECOVERED, true); + } + FAPI_TRY( pc::read_init_cal_error(i_target, l_err_data) ); l_err_data.extractToRight<TT::INIT_CAL_ERROR_WR_LEVEL, TT::CAL_ERROR_FIELD_LEN>(l_errors); @@ -405,7 +418,7 @@ fapi2::ReturnCode process_initial_cal_errors( const fapi2::Target<TARGET_TYPE_MC if ((l_rank_pairs == 0) || (l_errors == 0)) { FAPI_INF("Initial cal - no errors reported"); - return fapi2::current_err; + return fapi2::FAPI2_RC_SUCCESS; } // Get the DIMM which failed. We should only have one rank pair as we calibrate the diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit_training.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit_training.xml index 7b9f2017f..1dd454c20 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit_training.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit_training.xml @@ -84,7 +84,6 @@ <registerFfdc> <id>REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_STATUS</id> <scomRegister>MCA_DDRPHY_PC_INIT_CAL_ERROR_P0</scomRegister> - <scomRegister>MCA_DDRPHY_PC_ERROR_STATUS0_P0</scomRegister> <scomRegister>MCA_DDRPHY_DP16_RD_STATUS0_P0_0</scomRegister> <scomRegister>MCA_DDRPHY_DP16_RD_STATUS0_P0_1</scomRegister> <scomRegister>MCA_DDRPHY_DP16_RD_STATUS0_P0_2</scomRegister> @@ -106,8 +105,18 @@ <scomRegister>MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3</scomRegister> <scomRegister>MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4</scomRegister> </registerFfdc> -<hwpError> +<registerFfdc> + <id>REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_INFO</id> + <scomRegister>MCA_DDRPHY_APB_ERROR_STATUS0_P0</scomRegister> + <scomRegister>MCA_DDRPHY_APB_FIR_ERR0_P0</scomRegister> + <scomRegister>MCA_DDRPHY_APB_FIR_ERR1_P0</scomRegister> + <scomRegister>MCA_DDRPHY_APB_FIR_ERR2_P0</scomRegister> + <scomRegister>MCA_DDRPHY_APB_FIR_ERR3_P0</scomRegister> + <scomRegister>MCA_PHY0_DDRPHY_FIR_REG</scomRegister> +</registerFfdc> + +<hwpError> <rc>RC_MSS_DRAMINIT_TRAINING_MULTIPLE_ERRORS</rc> <description>Multiple training stesp failed for a given position within this calibration.</description> <ffdc>FAILED_STEPS</ffdc> @@ -384,4 +393,26 @@ </callout> </hwpError> +<hwpError> + <rc>RC_MSS_DRAMINIT_PC_ERROR_INFO</rc> + <description> + The PHY control has noted an error. The details of the error are contianed + in this error log. If these errors caused an operation to fail, a subsequent + error will be logged indicating the failure. + </description> + <ffdc>PC_ERROR0</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_INFO</id> + <target>TARGET_IN_ERROR</target> + </collectRegisterFfdc> + <callout> + <target>TARGET_IN_ERROR</target> + <priority>LOW</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> +</hwpError> + </hwpErrors> |