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author | Anusha Reddy Rangareddygari <anusrang@in.ibm.com> | 2016-03-16 13:35:33 +0100 |
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committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-02-23 14:47:40 -0500 |
commit | c09666bba7391f78dd12a92619506da81bfa315f (patch) | |
tree | a096456c235665687c4a3eea951896e032064439 /src/import | |
parent | 3eae384a982b6d35b1196f22aade47001c18d3b9 (diff) | |
download | talos-hostboot-c09666bba7391f78dd12a92619506da81bfa315f.tar.gz talos-hostboot-c09666bba7391f78dd12a92619506da81bfa315f.zip |
Level 2 HWPs for new IPL changes
Change-Id: I0b9b8e80f34de7bd962b686f91ebc504cda1ff34
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22103
Tested-by: Jenkins Server
Tested-by: PPE CI
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: Sunil Kumar <skumar8j@in.ibm.com>
Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36933
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import')
-rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H index e749e7296..60a24c60e 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H @@ -79,7 +79,12 @@ enum P9_SBE_CHIPLET_RESET_Public_Constants NET_CNTL1_HW_INIT_VALUE = 0x7200000000000000ull, MCGR2_CACHE_CNFG_SETTINGS = 0xF0001C0000000000ull, MCGR3_CACHE_CNFG_SETTINGS = 0xF4001C0000000000ull, - MCGR4_CACHE_CNFG_SETTINGS = 0xF8001C0000000000ull + MCGR4_CACHE_CNFG_SETTINGS = 0xF8001C0000000000ull, + REGIONS_EXCEPT_VITAL = 0x7FF, + SCAN_TYPES_EXCEPT_TIME_GPTR_REPR = 0xDCE, + SCAN_TYPES_TIME_GPTR_REPR = 0x230, + SCAN_RATIO_0X0 = 0x0, + SYNC_CONFIG_4TO1 = 0X0800000000000000 }; } |