Add workaround for DDRPHY ODT config register erratum (ODT2, ODT3 bits swapped)

Change-Id: If02e5e31c768c62bbdf37c15b5146bacaaf38d80
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36173
Dev-Ready: Louis Stermole <stermole@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Brent Wieman <bwieman@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36196
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

5 files changed, 177 insertions, 1 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors_manual.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors_manual.H
index 078e7682d..54b594bbb 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors_manual.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors_manual.H
@@ -278,7 +278,30 @@ inline bool chip_ec_feature_blue_waterfall_adjust(const fapi2::Target<T>& i_targ
     return (l_value != 0) && (l_do_value == fapi2::ENUM_ATTR_DO_BLUE_WATERFALL_ADJUST_YES);
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_CHIP_EC_FEATURE_MSS_WR_VREF or ATTR_DO_MSS_WR_VREF: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_CHIP_EC_FEATURE_MSS_BLUE_WATERFALL_ADJUST or ATTR_DO_BLUE_WATERFALL_ADJUST: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    fapi2::Assert(false);
+    return false;
+}
+
+///
+/// @brief ATTR_CHIP_EC_FEATURE_MSS_ODT_CONFIG getter
+/// @tparam T the fapi2 target type of the target
+/// @param[in] const ref to the target
+/// @return bool true iff feature is enabled
+///
+template< fapi2::TargetType T >
+inline bool chip_ec_feature_mss_odt_config(const fapi2::Target<T>& i_target)
+{
+    const auto l_chip = mss::find_target<fapi2::TARGET_TYPE_PROC_CHIP>(i_target);
+    uint8_t l_value = 0;
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_MSS_ODT_CONFIG, l_chip, l_value) );
+
+    return l_value != 0;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_CHIP_EC_FEATURE_MSS_ODT_CONFIG: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     fapi2::Assert(false);
     return false;
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
index 75d85d165..d34b7242f 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
@@ -49,6 +49,7 @@
 #include <lib/workarounds/dp16_workarounds.H>
 #include <lib/workarounds/wr_vref_workarounds.H>
 #include <lib/dimm/ddr4/latch_wr_vref.H>
+#include <lib/workarounds/seq_workarounds.H>
 
 #include <lib/utils/bit_count.H>
 #include <lib/utils/find.H>
@@ -766,6 +767,7 @@ fapi2::ReturnCode phy_scominit(const fapi2::Target<TARGET_TYPE_MCBIST>& i_target
         FAPI_TRY( mss::workarounds::dp16::dqs_polarity(p) );
         FAPI_TRY( mss::workarounds::dp16::rd_dia_config5(p) );
         FAPI_TRY( mss::workarounds::dp16::dqsclk_offset(p) );
+        FAPI_TRY( mss::workarounds::seq::odt_config(p) );
     }
 
 fapi_try_exit:
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/seq_workarounds.C b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/seq_workarounds.C
index 2aa8be039..53c212f91 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/seq_workarounds.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/seq_workarounds.C
@@ -22,3 +22,90 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
+
+///
+/// @file workarounds/seq_workarounds.C
+/// @brief Workarounds for the SEQ logic blocks
+/// Workarounds are very deivce specific, so there is no attempt to generalize
+/// this code in any way.
+///
+// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com>
+// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com>
+// *HWP Team: Memory
+// *HWP Level: 2
+// *HWP Consumed by: FSP:HB
+
+#include <fapi2.H>
+#include <p9_mc_scom_addresses.H>
+
+#include <lib/utils/scom.H>
+#include <lib/workarounds/seq_workarounds.H>
+
+namespace mss
+{
+
+namespace workarounds
+{
+
+namespace seq
+{
+
+///
+/// @brief ODT Config workaround
+/// For Nimbus DD1, ODT2 and ODT3 bits are swapped in each of the PHY config registers
+/// @param[in] i_target the fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+/// @note This function is called during the phy scom init procedure, after the initfile is
+/// processed.
+///
+fapi2::ReturnCode odt_config( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target )
+{
+    // skip the workaroud if attribute is not set
+    if (! mss::chip_ec_feature_mss_odt_config(i_target) )
+    {
+        return fapi2::FAPI2_RC_SUCCESS;
+    }
+
+    FAPI_INF("Running ODT Config workaround on %s", mss::c_str(i_target));
+
+    std::vector<fapi2::buffer<uint64_t>> l_read;
+
+    static const std::vector<uint64_t> ODT_REGS =
+    {
+        MCA_DDRPHY_SEQ_ODT_RD_CONFIG0_P0, MCA_DDRPHY_SEQ_ODT_RD_CONFIG1_P0,
+        MCA_DDRPHY_SEQ_ODT_WR_CONFIG0_P0, MCA_DDRPHY_SEQ_ODT_WR_CONFIG1_P0
+    };
+
+    FAPI_TRY(mss::scom_suckah(i_target, ODT_REGS, l_read));
+
+    for (auto& l_data : l_read)
+    {
+        // Note these bit positions are the same in RD_CONFIG* and WR_CONFIG*
+        constexpr uint64_t EVEN_RANK_ODT2 = 50;
+        constexpr uint64_t EVEN_RANK_ODT3 = 51;
+        constexpr uint64_t ODD_RANK_ODT2 = 58;
+        constexpr uint64_t ODD_RANK_ODT3 = 59;
+
+        bool l_odt2 = 0;
+        bool l_odt3 = 0;
+
+        // swap even rank ODT2 and ODT3
+        l_odt2 = l_data.getBit<EVEN_RANK_ODT2>();
+        l_odt3 = l_data.getBit<EVEN_RANK_ODT3>();
+        l_data.writeBit<EVEN_RANK_ODT2>(l_odt3).writeBit<EVEN_RANK_ODT3>(l_odt2);
+        // swap odd rank ODT2 and ODT3
+        l_odt2 = l_data.getBit<ODD_RANK_ODT2>();
+        l_odt3 = l_data.getBit<ODD_RANK_ODT3>();
+        l_data.writeBit<ODD_RANK_ODT2>(l_odt3).writeBit<ODD_RANK_ODT3>(l_odt2);
+    }
+
+    FAPI_TRY(mss::scom_blastah(i_target, ODT_REGS, l_read));
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+
+} // close namespace seq
+} // close namespace workarounds
+} // close namespace mss
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/seq_workarounds.H b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/seq_workarounds.H
index 7bc2ac898..0c72fbeb2 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/seq_workarounds.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/seq_workarounds.H
@@ -22,3 +22,47 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
+
+///
+/// @file workarounds/seq_workarounds.H
+/// @brief Workarounds for the SEQ logic blocks
+/// Workarounds are very deivce specific, so there is no attempt to generalize
+/// this code in any way.
+///
+// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com>
+// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com>
+// *HWP Team: Memory
+// *HWP Level: 2
+// *HWP Consumed by: FSP:HB
+
+#ifndef _MSS_WORKAROUNDS_SEQ_H_
+#define _MSS_WORKAROUNDS_SEQ_H_
+
+#include <fapi2.H>
+#include <p9_mc_scom_addresses.H>
+#include <mss_attribute_accessors.H>
+
+namespace mss
+{
+
+namespace workarounds
+{
+
+namespace seq
+{
+
+///
+/// @brief ODT Config workaround
+/// For Nimbus DD1, ODT2 and ODT3 bits are swapped in each of the PHY config registers
+/// @param[in] i_target the fapi2 target of the port
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+/// @note This function is called during the phy scom init procedure, after the initfile is
+/// processed.
+///
+fapi2::ReturnCode odt_config( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target );
+
+} // close namespace seq
+} // close namespace workarounds
+} // close namespace mss
+
+#endif
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
index 15b2ea91b..43bb31830 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
@@ -2304,6 +2304,25 @@
   </attribute>
 
   <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_MSS_ODT_CONFIG</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      For Nimbus pre DD2.** we need to swap ODT2 and ODT3 values in the
+      DDRPHY_SEQ_ODT_RD/WR_CONFIG registers due to a PHY erratum.
+      Post DD2.** will have a hardware enabled fix for this (HW389360).
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+  <attribute>
     <id>ATTR_CHIP_EC_FEATURE_MSS_BLUE_WATERFALL_ADJUST</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
@@ -2354,6 +2373,7 @@
       </chip>
     </chipEcFeature>
   </attribute>
+
   <!-- ******************************************************************** -->
   <!-- End Memory Section                                                   -->
   <!-- ******************************************************************** -->