p9_pcie_scominit procedure update to addresss PHY issues

Change-Id: I4304e754056a741b250ea2861cd9afef529a50b0
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34521
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
CMVC-Coreq: 1014186
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34523
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

4 files changed, 300 insertions, 86 deletions

diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.C b/src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.C
index c184f0300..55d9a8f4c 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -97,17 +97,23 @@ fapi2::ReturnCode p9_pcie_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_C
     uint8_t l_attr_proc_pcie_iovalid_enable = 0;
     uint8_t l_attr_proc_pcie_refclock_enable = 0;
     fapi2::buffer<uint64_t> l_buf = 0;
+    fapi2::buffer<uint64_t> l_buf2 = 0;
     unsigned char l_pec_id = 0;
     auto l_pec_chiplets_vec = i_target.getChildren<fapi2::TARGET_TYPE_PEC>();
     uint32_t l_pcs_config_mode[NUM_PCS_CONFIG] = {PCS_CONFIG_MODE0, PCS_CONFIG_MODE1, PCS_CONFIG_MODE2, PCS_CONFIG_MODE3};
     uint8_t l_pcs_cdr_gain[NUM_PCS_CONFIG] = {0};
-    uint16_t l_pcs_loff_control[NUM_PCS_CONFIG] = {0};
-    uint16_t l_pcs_vga_control_register3[NUM_PCS_CONFIG] = {0};
+    uint8_t l_pcs_pk_init[NUM_PCS_CONFIG][NUM_PCIE_LANES] = {0};
+    uint8_t l_pcs_init_gain[NUM_PCS_CONFIG][NUM_PCIE_LANES] = {0};
+    uint8_t l_pcs_sigdet_lvl[NUM_PCS_CONFIG] = {0};
     uint16_t l_pcs_m_cntl[NUM_M_CONFIG] = {0};
     uint8_t l_pcs_rot_cntl_cdr_lookahead = 0;
     uint8_t l_pcs_rot_cntl_cdr_ssc = 0;
+    uint8_t l_pcs_rot_cntl_extel = 0;
+    uint8_t l_pcs_rot_cntl_rst_fw = 0;
+    uint8_t l_pcs_rx_dfe_fddc = 0;
     uint8_t l_attr_8 = 0;
     uint16_t l_attr_16 = 0;
+    uint32_t l_poll_counter; //Number of iterations while polling for PLLA and PLLB Port Ready Status
 
     FAPI_DBG("target vec size: %#x", l_pec_chiplets_vec.size());
     FAPI_DBG("l_buf: %#x", l_buf());
@@ -170,6 +176,59 @@ fapi2::ReturnCode p9_pcie_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_C
         FAPI_DBG("pec%i: %#lx", l_pec_id, l_buf());
         FAPI_TRY(fapi2::putScom(l_pec_chiplets, PEC_CPLT_CONF1_CLEAR, l_buf));
 
+        FAPI_TRY(fapi2::delay(PMA_RESET_NANO_SEC_DELAY, PMA_RESET_CYC_DELAY), "fapiDelay error.");
+
+        l_buf = 0;
+        FAPI_TRY(l_buf.insertFromRight(1, PEC_IOP_PMA_RESET_START_BIT, 1));
+        FAPI_DBG("pec%i: %#lx", l_pec_id, l_buf());
+        FAPI_TRY(fapi2::putScom(l_pec_chiplets, PEC_CPLT_CONF1_OR, l_buf));
+
+        FAPI_TRY(fapi2::delay(PMA_RESET_NANO_SEC_DELAY, PMA_RESET_CYC_DELAY), "fapiDelay error.");
+
+        l_buf = 0;
+        FAPI_TRY(l_buf.insertFromRight(1, PEC_IOP_PMA_RESET_START_BIT, 1));
+        FAPI_DBG("pec%i: %#lx", l_pec_id, l_buf());
+        FAPI_TRY(fapi2::putScom(l_pec_chiplets, PEC_CPLT_CONF1_CLEAR, l_buf));
+
+        FAPI_DBG("pec%i: Poll for PRTREADY status on PLLA and PLLB.", l_pec_id);
+        l_poll_counter = 0; //Reset poll counter
+
+        while (l_poll_counter < MAX_NUM_POLLS)
+        {
+            l_poll_counter++;
+            FAPI_TRY(fapi2::delay(PMA_RESET_NANO_SEC_DELAY, PMA_RESET_CYC_DELAY), "fapiDelay error.");
+
+            //Read PLLA VCO Course Calibration Register into l_buf
+            FAPI_TRY(fapi2::getScom(l_pec_chiplets, PEC_IOP_PLLA_VCO_COURSE_CAL_REGISTER1, l_buf),
+                     "Could not retrieve IOP PLLA VCO Course Calibration Register 1.");
+            FAPI_DBG("pec%i: %#lx", l_pec_id, l_buf());
+
+            //Read PLLB VCO Course Calibration Register into l_buf
+            FAPI_TRY(fapi2::getScom(l_pec_chiplets, PEC_IOP_PLLB_VCO_COURSE_CAL_REGISTER1, l_buf2),
+                     "Could not retrieve IOP PLLB VCO Course Calibration Register 1.");
+            FAPI_DBG("pec%i: %#lx", l_pec_id, l_buf2());
+
+            //Check PRTEADY PLLA and PLLB status bit
+            if ((l_buf.getBit(PEC_IOP_HSS_PORT_READY_START_BIT) || l_buf2.getBit(PEC_IOP_HSS_PORT_READY_START_BIT)))
+            {
+
+                FAPI_DBG("pec%i: HSS Port is ready.", l_pec_id);
+                break;
+            }
+        }
+
+        FAPI_DBG("pec%i: IOP HSS Port Ready status (poll counter = %d).", l_pec_id, l_poll_counter);
+
+        FAPI_ASSERT(l_poll_counter < MAX_NUM_POLLS,
+                    fapi2::P9_IOP_HSS_PORT_NOT_READY()
+                    .set_TARGET(l_pec_chiplets)
+                    .set_PLLA_ADDR(PEC_IOP_PLLA_VCO_COURSE_CAL_REGISTER1)
+                    .set_PLLA_DATA(l_buf)
+                    .set_PLLB_ADDR(PEC_IOP_PLLB_VCO_COURSE_CAL_REGISTER1)
+                    .set_PLLB_DATA(l_buf2),
+                    "pec%i: IOP HSS Port Ready status is not set!", l_pec_id);
+
+
         // Phase1 init step 5 (Set FIR action0)
         l_buf = 0;
         FAPI_DBG("pec%i: %#lx", l_pec_id, l_buf());
@@ -186,38 +245,45 @@ fapi2::ReturnCode p9_pcie_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_C
         FAPI_TRY(fapi2::putScom(l_pec_chiplets, PEC_FIR_MASK_REG, l_buf));
 
         // Phase1 init step 8-11 (Config 0 - 3)
-        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_PCIE_PCS_RX_CDR_GAIN, l_pec_chiplets,
-                               l_pcs_cdr_gain));
-        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_PCIE_PCS_RX_LOFF_CONTROL, l_pec_chiplets,
-                               l_pcs_loff_control));
-        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_PCIE_PCS_RX_VGA_CONTRL_REGISTER3, l_pec_chiplets,
-                               l_pcs_vga_control_register3));
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_PCIE_PCS_RX_CDR_GAIN, l_pec_chiplets, l_pcs_cdr_gain));
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_PCIE_PCS_RX_INIT_GAIN, l_pec_chiplets, l_pcs_init_gain));
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_PCIE_PCS_RX_PK_INIT, l_pec_chiplets, l_pcs_pk_init));
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_PCIE_PCS_RX_SIGDET_LVL, l_pec_chiplets, l_pcs_sigdet_lvl));
 
         for (int i = 0; i < NUM_PCS_CONFIG; i++)
         {
             // RX Config Mode
             l_buf = 0;
             FAPI_TRY(l_buf.insertFromRight(l_pcs_config_mode[i], 48, 16));
-            FAPI_DBG("pec%i: %#lx", l_pec_id, l_buf());
+            FAPI_DBG("pec%i cfg%i: %#lx", l_pec_id, i, l_buf());
             FAPI_TRY(fapi2::putScom(l_pec_chiplets, PEC_PCS_RX_CONFIG_MODE_REG, l_buf));
 
             // RX CDR GAIN
             FAPI_TRY(fapi2::getScom(l_pec_chiplets, PEC_PCS_RX_CDR_GAIN_REG, l_buf));
             FAPI_TRY(l_buf.insertFromRight(l_pcs_cdr_gain[i], 56, 8));
-            FAPI_DBG("pec%i: %#lx", l_pec_id, l_buf());
+            FAPI_DBG("pec%i cfg%i: %#lx", l_pec_id, i, l_buf());
             FAPI_TRY(fapi2::putScom(l_pec_chiplets, PEC_PCS_RX_CDR_GAIN_REG, l_buf));
 
-            // RX LOFF CONTROL
-            l_buf = 0;
-            FAPI_TRY(l_buf.insertFromRight(l_pcs_loff_control[i], 48, 16));
-            FAPI_DBG("pec%i: %#lx", l_pec_id, l_buf());
-            FAPI_TRY(fapi2::putScom(l_pec_chiplets, PEC_PCS_RX_LOFF_CONTROL_REG, l_buf));
-
-            // RX VGA CONTROL REGISTER3
-            l_buf = 0;
-            FAPI_TRY(l_buf.insertFromRight(l_pcs_vga_control_register3[i], 48, 16));
-            FAPI_DBG("pec%i: %#lx", l_pec_id, l_buf());
-            FAPI_TRY(fapi2::putScom(l_pec_chiplets, PEC_PCS_RX_VGA_CONTROL3_REG, l_buf));
+            for  (int l_lane = 0; l_lane < NUM_PCIE_LANES; l_lane++)
+            {
+                // RX INITGAIN
+                FAPI_TRY(fapi2::getScom(l_pec_chiplets, RX_VGA_CTRL3_REGISTER[l_lane], l_buf));
+                FAPI_TRY(l_buf.insertFromRight(l_pcs_init_gain[i][l_lane], 48, 5));
+                FAPI_DBG("pec%i cfg%i lane%i: %#lx", l_pec_id, i, l_lane, l_buf());
+                FAPI_TRY(fapi2::putScom(l_pec_chiplets, RX_VGA_CTRL3_REGISTER[l_lane], l_buf));
+
+                // RX PKINIT
+                FAPI_TRY(fapi2::getScom(l_pec_chiplets, RX_LOFF_CNTL_REGISTER[l_lane], l_buf));
+                FAPI_TRY(l_buf.insertFromRight(l_pcs_pk_init[i][l_lane], 58, 6));
+                FAPI_DBG("pec%i cfg%i lane%i: %#lx", l_pec_id, i, l_lane, l_buf());
+                FAPI_TRY(fapi2::putScom(l_pec_chiplets, RX_LOFF_CNTL_REGISTER[l_lane], l_buf));
+            }
+
+            // RX SIGDET LVL
+            FAPI_TRY(fapi2::getScom(l_pec_chiplets, PEC_PCS_RX_SIGDET_CONTROL_REG, l_buf));
+            FAPI_TRY(l_buf.insertFromRight(l_pcs_sigdet_lvl[i], 59, 5));
+            FAPI_DBG("pec%i cfg%i: %#lx", l_pec_id, i, l_buf());
+            FAPI_TRY(fapi2::putScom(l_pec_chiplets, PEC_PCS_RX_SIGDET_CONTROL_REG, l_buf));
         }
 
         // Phase1 init step 12 (RX Rot Cntl CDR Lookahead Disabled,SSC Disabled)
@@ -225,9 +291,15 @@ fapi2::ReturnCode p9_pcie_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_C
                                l_pcs_rot_cntl_cdr_lookahead));
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_PCIE_PCS_RX_ROT_CDR_SSC, l_pec_chiplets,
                                l_pcs_rot_cntl_cdr_ssc));
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_PCIE_PCS_RX_ROT_EXTEL, l_pec_chiplets,
+                               l_pcs_rot_cntl_extel));
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_PCIE_PCS_RX_ROT_RST_FW, l_pec_chiplets,
+                               l_pcs_rot_cntl_rst_fw));
         FAPI_TRY(fapi2::getScom(l_pec_chiplets, PEC_PCS_RX_ROT_CNTL_REG, l_buf));
         FAPI_TRY(l_buf.insertFromRight(l_pcs_rot_cntl_cdr_lookahead, 55, 1));
         FAPI_TRY(l_buf.insertFromRight(l_pcs_rot_cntl_cdr_ssc, 63, 1));
+        FAPI_TRY(l_buf.insertFromRight(l_pcs_rot_cntl_extel, 59, 1));
+        FAPI_TRY(l_buf.insertFromRight(l_pcs_rot_cntl_rst_fw, 62, 1));
         FAPI_DBG("pec%i: %#lx", l_pec_id, l_buf());
         FAPI_TRY(fapi2::putScom(l_pec_chiplets, PEC_PCS_RX_ROT_CNTL_REG, l_buf));
 
@@ -252,52 +324,39 @@ fapi2::ReturnCode p9_pcie_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_C
                                        PEC_PCS_TX_DCLCK_ROTATOR_REG,
                                        48, 16);
 
-        // Phase1 init step 17 (TX FIFO Config Offset)
-        SET_REG_RMW_WITH_SINGLE_ATTR_8(fapi2::ATTR_PROC_PCIE_PCS_TX_FIFO_CONFIG_OFFSET,
-                                       PEC_PCS_TX_FIFO_CONFIG_OFFSET_REG,
-                                       59, 5);
-
-        // Phase1 init step 18 (TX PCIe Receiver Detect Control Register 1)
+        // Phase1 init step 17 (TX PCIe Receiver Detect Control Register 1)
         SET_REG_WR_WITH_SINGLE_ATTR_16(fapi2::ATTR_PROC_PCIE_PCS_TX_PCIE_RECV_DETECT_CNTL_REG1,
                                        PEC_PCS_TX_PCIE_REC_DETECT_CNTL1_REG,
                                        48, 16);
 
-        // Phase1 init step 19 (TX PCIe Receiver Detect Control Register 2)
+        // Phase1 init step 18 (TX PCIe Receiver Detect Control Register 2)
         SET_REG_WR_WITH_SINGLE_ATTR_16(fapi2::ATTR_PROC_PCIE_PCS_TX_PCIE_RECV_DETECT_CNTL_REG2,
                                        PEC_PCS_TX_PCIE_REC_DETECT_CNTL2_REG,
                                        48, 16);
 
-        // Phase1 init step 20 (TX Power Sequence Enable)
+        // Phase1 init step 19 (TX Power Sequence Enable)
         SET_REG_RMW_WITH_SINGLE_ATTR_8(fapi2::ATTR_PROC_PCIE_PCS_TX_POWER_SEQ_ENABLE,
                                        PEC_PCS_TX_POWER_SEQ_ENABLE_REG,
                                        56, 7);
 
-        // Phase1 init step 21 (RX Phase Rotator Control)
-        SET_REG_WR_WITH_SINGLE_ATTR_16(fapi2::ATTR_PROC_PCIE_PCS_RX_PHASE_ROTATOR_CNTL,
-                                       PEC_PCS_RX_ROT_CNTL_REG,
-                                       48, 16);
-
-        // Phase1 init step 22 (RX VGA Control Register 1)
+        // Phase1 init step 20 (RX VGA Control Register 1)
         SET_REG_WR_WITH_SINGLE_ATTR_16(fapi2::ATTR_PROC_PCIE_PCS_RX_VGA_CNTL_REG1,
                                        PEC_PCS_RX_VGA_CONTROL1_REG,
                                        48, 16);
 
-        // Phase1 init step 23 (RX VGA Control Register 2)
+        // Phase1 init step 21 (RX VGA Control Register 2)
         SET_REG_WR_WITH_SINGLE_ATTR_16(fapi2::ATTR_PROC_PCIE_PCS_RX_VGA_CNTL_REG2,
                                        PEC_PCS_RX_VGA_CONTROL2_REG,
                                        48, 16);
 
-        // Phase1 init step 24 (RX SIGDET Control)
-        SET_REG_WR_WITH_SINGLE_ATTR_16(fapi2::ATTR_PROC_PCIE_PCS_RX_SIGDET_CNTL,
-                                       PEC_PCS_RX_SIGDET_CONTROL_REG,
-                                       48, 16);
-        // Phase1 init step 25
-        l_buf = 0;
-        FAPI_TRY(l_buf.insertFromRight(1, PEC_IOP_PIPE_RESET_START_BIT, 1));
+        // Phase1 init step 22 (RX DFE Func Control Register 1)
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_PCIE_PCS_RX_DFE_FDDC, l_pec_chiplets, l_pcs_rx_dfe_fddc));
+        FAPI_TRY(fapi2::getScom(l_pec_chiplets, PEC_IOP_RX_DFE_FUNC_REGISTER1, l_buf));
+        FAPI_TRY(l_buf.insertFromRight(l_pcs_rx_dfe_fddc, 50, 1));
         FAPI_DBG("pec%i: %#lx", l_pec_id, l_buf());
-        FAPI_TRY(fapi2::putScom(l_pec_chiplets, PEC_CPLT_CONF1_CLEAR, l_buf));
+        FAPI_TRY(fapi2::putScom(l_pec_chiplets, PEC_IOP_RX_DFE_FUNC_REGISTER1, l_buf));
 
-        // Phase1 init step 26 (PCS System Control)
+        // Phase1 init step 23 (PCS System Control)
         SET_REG_RMW_WITH_SINGLE_ATTR_16(fapi2::ATTR_PROC_PCIE_PCS_SYSTEM_CNTL,
                                         PEC_PCS_SYS_CONTROL_REG,
                                         55, 9);
@@ -305,25 +364,37 @@ fapi2::ReturnCode p9_pcie_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_C
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_PCIE_PCS_M_CNTL, l_pec_chiplets,
                                l_pcs_m_cntl));
 
-        // Phase1 init step 27 (PCS M1 Control)
+        // Phase1 init step 24 (PCS M1 Control)
         SET_REG_RMW(l_pcs_m_cntl[0],
                     PEC_PCS_M1_CONTROL_REG,
                     55, 9);
 
-        // Phase1 init step 28 (PCS M2 Control)
+        // Phase1 init step 25 (PCS M2 Control)
         SET_REG_RMW(l_pcs_m_cntl[1],
                     PEC_PCS_M1_CONTROL_REG,
                     55, 9);
 
-        // Phase1 init step 29 (PCS M3 Control)
+        // Phase1 init step 26 (PCS M3 Control)
         SET_REG_RMW(l_pcs_m_cntl[2],
                     PEC_PCS_M1_CONTROL_REG,
                     55, 9);
 
-        // Phase1 init step 30 (PCS M4 Control)
+        // Phase1 init step 27 (PCS M4 Control)
         SET_REG_RMW(l_pcs_m_cntl[3],
                     PEC_PCS_M1_CONTROL_REG,
                     55, 9);
+
+        //Delay a minimum of 200ns to allow prior SCOM programming to take effect
+        FAPI_TRY(fapi2::delay(PMA_RESET_NANO_SEC_DELAY, PMA_RESET_CYC_DELAY), "fapiDelay error.");
+
+        // Phase1 init step 28
+        l_buf = 0;
+        FAPI_TRY(l_buf.insertFromRight(1, PEC_IOP_PIPE_RESET_START_BIT, 1));
+        FAPI_DBG("pec%i: %#lx", l_pec_id, l_buf());
+        FAPI_TRY(fapi2::putScom(l_pec_chiplets, PEC_CPLT_CONF1_CLEAR, l_buf));
+
+        //Delay a minimum of 300ns for reset to complete. Inherent delay before deasserting PCS PIPE Reset is enough here.
+
     }
 
     FAPI_INF("End");
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.H b/src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.H
index 4a4fa44d4..a750703ce 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.H
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -88,6 +88,7 @@ typedef fapi2::ReturnCode (*p9_pcie_scominit_FP_t) (const fapi2::Target<fapi2::T
 //-----------------------------------------------------------------------------------
 
 const uint8_t NUM_PCS_CONFIG = 4;
+const uint8_t NUM_PCIE_LANES = 16;
 const uint8_t NUM_M_CONFIG = 4;
 const uint8_t PEC0_IOP_CONFIG_START_BIT = 13;
 const uint8_t PEC1_IOP_CONFIG_START_BIT = 14;
@@ -104,12 +105,63 @@ const uint8_t PEC2_IOP_IOVALID_ENABLE_START_BIT = 4;
 const uint8_t PEC_IOP_REFCLOCK_ENABLE_START_BIT = 32;
 const uint8_t PEC_IOP_PMA_RESET_START_BIT = 29;
 const uint8_t PEC_IOP_PIPE_RESET_START_BIT = 28;
-
-const uint32_t PCS_CONFIG_MODE0 = 0xA0006;
+const uint8_t PEC_IOP_HSS_PORT_READY_START_BIT = 58;
+
+const uint64_t  PEC_IOP_PLLA_VCO_COURSE_CAL_REGISTER1 = 0x800005010D010C3F;
+const uint64_t  PEC_IOP_PLLB_VCO_COURSE_CAL_REGISTER1 = 0x800005410D010C3F;
+const uint64_t  PEC_IOP_RX_DFE_FUNC_REGISTER1 = 0x8000049F0D010C3F;
+const uint64_t  PEC_IOP_RX_DFE_FUNC_REGISTER2 = 0x800004A00D010C3F;
+
+const uint64_t  RX_VGA_CTRL3_REGISTER[NUM_PCIE_LANES] =
+{
+    0x8000008D0D010C3F,
+    0x800000CD0D010C3F,
+    0x8000018D0D010C3F,
+    0x800001CD0D010C3F,
+    0x8000028D0D010C3F,
+    0x800002CD0D010C3F,
+    0x8000038D0D010C3F,
+    0x800003CD0D010C3F,
+    0x8000088D0D010C3F,
+    0x800008CD0D010C3F,
+    0x8000098D0D010C3F,
+    0x800009CD0D010C3F,
+    0x80000A8D0D010C3F,
+    0x80000ACD0D010C3F,
+    0x80000B8D0D010C3F,
+    0x80000BCD0D010C3F,
+};
+
+const uint64_t  RX_LOFF_CNTL_REGISTER[NUM_PCIE_LANES] =
+{
+    0x800000A60D010C3F,
+    0x800000E60D010C3F,
+    0x800001A60D010C3F,
+    0x800001E60D010C3F,
+    0x800002A60D010C3F,
+    0x800002E60D010C3F,
+    0x800003A60D010C3F,
+    0x800003E60D010C3F,
+    0x800008A60D010C3F,
+    0x800008E60D010C3F,
+    0x800009A60D010C3F,
+    0x800009E60D010C3F,
+    0x80000AA60D010C3F,
+    0x80000AE60D010C3F,
+    0x80000BA60D010C3F,
+    0x80000BE60D010C3F,
+
+};
+
+const uint32_t PCS_CONFIG_MODE0 = 0xA006;
 const uint32_t PCS_CONFIG_MODE1 = 0xA805;
 const uint32_t PCS_CONFIG_MODE2 = 0xB071;
 const uint32_t PCS_CONFIG_MODE3 = 0xB870;
 
+const uint32_t MAX_NUM_POLLS = 100; //Maximum number of iterations (So, 400ns * 100 = 40us before timeout)
+const uint64_t PMA_RESET_NANO_SEC_DELAY = 400; //400ns to wait for PMA RESET to go through
+const uint64_t PMA_RESET_CYC_DELAY = 400; //400ns to wait for PMA RESET to go through
+
 extern "C" {
 
 //-----------------------------------------------------------------------------------
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_pcie_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_pcie_attributes.xml
index c8d4b4920..cf69864e8 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/p9_pcie_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_pcie_attributes.xml
@@ -5,7 +5,7 @@
 <!--                                                                        -->
 <!-- OpenPOWER HostBoot Project                                             -->
 <!--                                                                        -->
-<!-- Contributors Listed Below - COPYRIGHT 2015,2016                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2017                        -->
 <!-- [+] International Business Machines Corp.                              -->
 <!--                                                                        -->
 <!--                                                                        -->
@@ -34,6 +34,16 @@
       consumer: p9_pcie_scominit
       firmware notes:
         Encoded PCIE IOP lane configuration
+        PEC0 - CFG[0:1] => CFG[0:1] = PHB0(0:15)
+        PEC1 - CFG[0:3] => CFG[0:1] = PHB1(0:7)
+        		=> CFG[2:3] = PHB2(0:7)
+        PEC2 - CFG[0:5] => CFG[0:1] = 0b00; CFG[2:3] = PHB3(0:15)
+        				    CFG[4:5] = don't care
+        		=> CFG[0:1] = 0b01; CFG[2:3] = PHB3(0:7)
+        		   		    CFG[4:5] = PHB4(0:7)
+        		=> CFG[0:1] = 0b10; CFG[2:3] = PHB3(0:7)
+        		   		    CFG[4]   = PHB4(0:3)
+        		   		    CFG[5]   = PHB5(0:3)
     </description>
     <valueType>uint8</valueType>
     <platInit/>
@@ -49,6 +59,12 @@
       consumer: p9_pcie_scominit
       firmware notes:
         Encoded PCIE IOP swap configuration
+        PEC0 - SWP[0]   => SWP[0] = PHB0(0:15)
+        PEC1 - SWP[0:1] => SWP[0] = PHB1(0:7)
+        		=> SWP[1] = PHB2(0:7)
+        PEC2 - SWP[0:2] => SWP[0] = PHB3(0:7) or PHB3(0:15)
+        		=> SWP[1] = PHB4(0:3) or PHB4(0:7) or don't care if disabled
+        		=> SWP[2] = PHB5(0:3) or don't care if disabled
     </description>
     <valueType>uint8</valueType>
     <platInit/>
@@ -62,6 +78,14 @@
       PCIE iovalid enable valid mask
       creator: platform
       consumer: p9_pcie_scominit
+      firmware notes:
+        Encoded PCIE IO Valid configuration
+        PEC0 - IOVALID[0]   => IOVALID[0] = PHB0
+        PEC1 - IOVALID[0:1] => IOVALID[0] = PHB1
+        		    => IOVALID[1] = PHB2
+        PEC2 - IOVALID[0:2] => IOVALID[0] = PHB3
+        		    => IOVALID[1] = PHB4
+        		    => IOVALID[2] = PHB5
     </description>
     <valueType>uint8</valueType>
     <platInit/>
@@ -75,6 +99,9 @@
       PCIE refclock enable valid mask
       creator: platform
       consumer: p9_pcie_scominit
+      firmware notes:
+        Only one REFCLK enable bit exists across all PECs. There is no granualarity
+        to control REFCLK enables on a per PHB basis.
     </description>
     <valueType>uint8</valueType>
     <platInit/>
@@ -237,40 +264,61 @@
   </attribute>
   <!-- ********************************************************************* -->
   <attribute>
-    <id>ATTR_PROC_PCIE_PCS_RX_LOFF_CONTROL</id>
+    <id>ATTR_PROC_PCIE_PCS_RX_PK_INIT</id>
     <targetType>TARGET_TYPE_PEC</targetType>
     <description>
-      PCS rx loff control
+      PCS rx vga peak init value
       creator: platform
       consumer: p9_pcie_scominit
       firmware notes:
-        The value of rx loff control for PCS.
+        The value of rx vga peak init for PCS.
         Array index: Configuration number
         index 0~3 for CONFIG0~3
+        lane 0~15 for each PCIE Lane
     </description>
-    <valueType>uint16</valueType>
-    <array>4</array>
+    <valueType>uint8</valueType>
+    <array>4 16</array>
     <platInit/>
     <persistRuntime/>
   </attribute>
   <!-- ********************************************************************* -->
   <attribute>
-    <id>ATTR_PROC_PCIE_PCS_RX_VGA_CONTRL_REGISTER3</id>
+    <id>ATTR_PROC_PCIE_PCS_RX_INIT_GAIN</id>
     <targetType>TARGET_TYPE_PEC</targetType>
     <description>
-      PCS rx vga control register3
+      PCS rx vga gain init value
       creator: platform
       consumer: p9_pcie_scominit
       firmware notes:
-        The value of rx vga control register3.
+        The value of rx vga gain init for PCS.
         Array index: Configuration number
         index 0~3 for CONFIG0~3
+        lane 0~15 for each PCIE Lane
     </description>
-    <valueType>uint16</valueType>
+    <valueType>uint8</valueType>
+    <array>4 16</array>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_PCIE_PCS_RX_SIGDET_LVL</id>
+    <targetType>TARGET_TYPE_PEC</targetType>
+    <description>
+      PCS rx sigdet lvl value
+      creator: platform
+      consumer: p9_pcie_scominit
+      firmware notes:
+        The value of rx sigdet lvl for PCS.
+        Array index: Configuration number
+        index 0~3 for CONFIG0~3
+    </description>
+    <valueType>uint8</valueType>
     <array>4</array>
     <platInit/>
     <persistRuntime/>
   </attribute>
+  <!-- ********************************************************************* -->
   <attribute>
     <id>ATTR_PROC_PCIE_PCS_RX_ROT_CDR_LOOKAHEAD</id>
     <targetType>TARGET_TYPE_PEC</targetType>
@@ -285,6 +333,7 @@
     <platInit/>
     <persistRuntime/>
   </attribute>
+  <!-- ********************************************************************* -->
   <attribute>
     <id>ATTR_PROC_PCIE_PCS_RX_ROT_CDR_SSC</id>
     <targetType>TARGET_TYPE_PEC</targetType>
@@ -299,47 +348,56 @@
     <platInit/>
     <persistRuntime/>
   </attribute>
+  <!-- ********************************************************************* -->
   <attribute>
-    <id>ATTR_PROC_PCIE_PCS_PCLCK_CNTL_PLLA</id>
+    <id>ATTR_PROC_PCIE_PCS_RX_ROT_EXTEL</id>
     <targetType>TARGET_TYPE_PEC</targetType>
     <description>
-      Value of PCS pclck control plla
+      Value of PCS RX ROT extel latch
       creator: platform
       consumer: p9_pcie_scominit
+      firmware notes:
+        0 for internal (default)
+        1 for external (freezes phase rotators)
     </description>
     <valueType>uint8</valueType>
     <platInit/>
     <persistRuntime/>
   </attribute>
+  <!-- ********************************************************************* -->
   <attribute>
-    <id>ATTR_PROC_PCIE_PCS_PCLCK_CNTL_PLLB</id>
+    <id>ATTR_PROC_PCIE_PCS_RX_ROT_RST_FW</id>
     <targetType>TARGET_TYPE_PEC</targetType>
     <description>
-      Value of PCS pclck control pllb
+      Value of PCS RX ROT rstfw latch
       creator: platform
       consumer: p9_pcie_scominit
+      firmware notes:
+        0 normal, flywheel is enabled (default)
+        1 assert reset to the phase rotator flywheel (disable the flywheel)
     </description>
     <valueType>uint8</valueType>
     <platInit/>
     <persistRuntime/>
   </attribute>
+  <!-- ********************************************************************* -->
   <attribute>
-    <id>ATTR_PROC_PCIE_PCS_TX_DCLCK_ROT</id>
+    <id>ATTR_PROC_PCIE_PCS_PCLCK_CNTL_PLLA</id>
     <targetType>TARGET_TYPE_PEC</targetType>
     <description>
-      Value of PCS tx dclck rotator override
+      Value of PCS pclck control plla
       creator: platform
       consumer: p9_pcie_scominit
     </description>
-    <valueType>uint16</valueType>
+    <valueType>uint8</valueType>
     <platInit/>
     <persistRuntime/>
   </attribute>
   <attribute>
-    <id>ATTR_PROC_PCIE_PCS_TX_FIFO_CONFIG_OFFSET</id>
+    <id>ATTR_PROC_PCIE_PCS_PCLCK_CNTL_PLLB</id>
     <targetType>TARGET_TYPE_PEC</targetType>
     <description>
-      Value of PCS tx fifo config offset
+      Value of PCS pclck control pllb
       creator: platform
       consumer: p9_pcie_scominit
     </description>
@@ -347,11 +405,12 @@
     <platInit/>
     <persistRuntime/>
   </attribute>
+  <!-- ********************************************************************* -->
   <attribute>
-    <id>ATTR_PROC_PCIE_PCS_TX_PCIE_RECV_DETECT_CNTL_REG1</id>
+    <id>ATTR_PROC_PCIE_PCS_TX_DCLCK_ROT</id>
     <targetType>TARGET_TYPE_PEC</targetType>
     <description>
-      Value of PCS tx pcie receiver detect control register 1
+      Value of PCS tx dclck rotator override
       creator: platform
       consumer: p9_pcie_scominit
     </description>
@@ -359,11 +418,12 @@
     <platInit/>
     <persistRuntime/>
   </attribute>
+  <!-- ********************************************************************* -->
   <attribute>
-    <id>ATTR_PROC_PCIE_PCS_TX_PCIE_RECV_DETECT_CNTL_REG2</id>
+    <id>ATTR_PROC_PCIE_PCS_TX_PCIE_RECV_DETECT_CNTL_REG1</id>
     <targetType>TARGET_TYPE_PEC</targetType>
     <description>
-      Value of PCS tx pcie receiver detect control register 2
+      Value of PCS tx pcie receiver detect control register 1
       creator: platform
       consumer: p9_pcie_scominit
     </description>
@@ -371,30 +431,33 @@
     <platInit/>
     <persistRuntime/>
   </attribute>
+  <!-- ********************************************************************* -->
   <attribute>
-    <id>ATTR_PROC_PCIE_PCS_TX_POWER_SEQ_ENABLE</id>
+    <id>ATTR_PROC_PCIE_PCS_TX_PCIE_RECV_DETECT_CNTL_REG2</id>
     <targetType>TARGET_TYPE_PEC</targetType>
     <description>
-      Value of PCS tx power sequence enable
+      Value of PCS tx pcie receiver detect control register 2
       creator: platform
       consumer: p9_pcie_scominit
     </description>
-    <valueType>uint8</valueType>
+    <valueType>uint16</valueType>
     <platInit/>
     <persistRuntime/>
   </attribute>
+  <!-- ********************************************************************* -->
   <attribute>
-    <id>ATTR_PROC_PCIE_PCS_RX_PHASE_ROTATOR_CNTL</id>
+    <id>ATTR_PROC_PCIE_PCS_TX_POWER_SEQ_ENABLE</id>
     <targetType>TARGET_TYPE_PEC</targetType>
     <description>
-      Value of PCS rx phase rotator control
+      Value of PCS tx power sequence enable
       creator: platform
       consumer: p9_pcie_scominit
     </description>
-    <valueType>uint16</valueType>
+    <valueType>uint8</valueType>
     <platInit/>
     <persistRuntime/>
   </attribute>
+  <!-- ********************************************************************* -->
   <attribute>
     <id>ATTR_PROC_PCIE_PCS_RX_VGA_CNTL_REG1</id>
     <targetType>TARGET_TYPE_PEC</targetType>
@@ -407,6 +470,7 @@
     <platInit/>
     <persistRuntime/>
   </attribute>
+  <!-- ********************************************************************* -->
   <attribute>
     <id>ATTR_PROC_PCIE_PCS_RX_VGA_CNTL_REG2</id>
     <targetType>TARGET_TYPE_PEC</targetType>
@@ -419,18 +483,20 @@
     <platInit/>
     <persistRuntime/>
   </attribute>
+  <!-- ********************************************************************* -->
   <attribute>
-    <id>ATTR_PROC_PCIE_PCS_RX_SIGDET_CNTL</id>
+    <id>ATTR_PROC_PCIE_PCS_RX_DFE_FDDC</id>
     <targetType>TARGET_TYPE_PEC</targetType>
     <description>
-      Value of PCS rx sigdet control
+      Value of PCS rx dfe func fddc control latch
       creator: platform
       consumer: p9_pcie_scominit
     </description>
-    <valueType>uint16</valueType>
+    <valueType>uint8</valueType>
     <platInit/>
     <persistRuntime/>
   </attribute>
+  <!-- ********************************************************************* -->
   <attribute>
     <id>ATTR_PROC_PCIE_PCS_SYSTEM_CNTL</id>
     <targetType>TARGET_TYPE_PEC</targetType>
@@ -443,6 +509,7 @@
     <platInit/>
     <persistRuntime/>
   </attribute>
+  <!-- ********************************************************************* -->
   <attribute>
     <id>ATTR_PROC_PCIE_PCS_M_CNTL</id>
     <targetType>TARGET_TYPE_PEC</targetType>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_pcie_scominit_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_pcie_scominit_errors.xml
index 7c1f74f56..c875c0530 100755
--- a/src/import/chips/p9/procedures/xml/error_info/p9_pcie_scominit_errors.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_pcie_scominit_errors.xml
@@ -5,7 +5,7 @@
 <!--                                                                        -->
 <!-- OpenPOWER HostBoot Project                                             -->
 <!--                                                                        -->
-<!-- Contributors Listed Below - COPYRIGHT 2016                             -->
+<!-- Contributors Listed Below - COPYRIGHT 2016,2017                        -->
 <!-- [+] International Business Machines Corp.                              -->
 <!--                                                                        -->
 <!--                                                                        -->
@@ -32,4 +32,28 @@
     </description>
     <ffdc>TARGET</ffdc>
   </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <rc>RC_P9_IOP_HSS_PORT_NOT_READY</rc>
+    <description>
+      Procedure: p9_pcie_scominit
+      IOP HSS Port PLLA and PLLB are not in ready state.
+      Cannot SCOM to PMA register space.
+    </description>
+    <ffdc>TARGET</ffdc>
+    <ffdc>PLLA_ADDR</ffdc>
+    <ffdc>PLLA_DATA</ffdc>
+    <ffdc>PLLB_ADDR</ffdc>
+    <ffdc>PLLB_DATA</ffdc>
+    <!-- Add procedure callout -->
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>LOW</priority>
+    </callout>
+    <!-- Add hw callout -->
+    <callout>
+      <target>TARGET</target>
+      <priority>HIGH</priority>
+    </callout>
+  </hwpError>
 </hwpErrors>