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authorRoland Veloz <rveloz@us.ibm.com>2018-12-13 11:26:42 -0600
committerChristian R. Geddes <crgeddes@us.ibm.com>2018-12-18 15:52:38 -0600
commita2833876dd0debf20aacfb9c6c5273cbdfc9039d (patch)
treeb9a5be7428f30dd5e21728cb248752a0018929d3 /src/import
parent36673e6d9525fcccb97a8232d2b54fb2bb05a1a8 (diff)
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HB Axone simics model changes to support DDIMM SPD i2c access
--- Added an I2C MUX target at engine 3, port 0, device address 0xE0 --- Added EEPROM_VPD_PRIMARY_INFO data to the DIMMs. This info also includes the I2C MUX target details to get to the MUX. EEPROM_VPD_PRIMARY_INFO fields: * byteAddrOffset set to 0x00 * chipCount set to 0x01 * maxMemorySizeKB set to 0x4000 (4 KB) * writeCycleTime set to 0x05 (5 ms) * writePageSize set to 0x20 --- Updated the I2C_BUS_SPEED_ARRAY attribute for target sys0node0proc0. Added speed 400 to array that corresponds to engine 3, port 0. Change-Id: Ia1965803a12f08e816b19d9d9a6fe2dfe3a2df36 RTC: 202358 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69835 Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Tested-by: Christian R. Geddes <crgeddes@us.ibm.com>
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