add omi attrs for omi dl config0

Change-Id: If906dba9415e641f4347dde76dd474e230c24bec
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78816
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78850
Reviewed-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>

4 files changed, 81 insertions, 4 deletions

diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9a_omi_train.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9a_omi_train.xml
new file mode 100644
index 000000000..623369508
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/attribute_info/p9a_omi_train.xml
@@ -0,0 +1,70 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/import/chips/p9/procedures/xml/attribute_info/p9a_omi_train.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER HostBoot Project                                             -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2019                             -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- -->
+<!-- @file p9a_omi_train.xml -->
+<!-- @brief Attribute xml for p9a_omi_train -->
+<!-- -->
+<!-- *HWP HWP Owner: Devon Baughen <devon.baughen1@ibm.com> -->
+<!-- *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> -->
+<!-- *HWP FW Owner: Daniel Crowell <dcrowell@us.ibm.com> -->
+<!-- *HWP Team: Memory -->
+<!-- *HWP Level: 2 -->
+<!-- *HWP Consumed by: FSP:HB -->
+<!-- -->
+
+<attributes>
+     <attribute>
+        <id>ATTR_OMI_DL_LN_REV_ENABLE</id>
+        <targetType>TARGET_TYPE_OMI</targetType>
+        <description>
+            The DL lane reversible enable bit in DL_CONFIG0_CFG (bit 38)
+        </description>
+        <valueType>uint8</valueType>
+        <enum>
+           ENABLED  = 0x01,
+           DISABLED = 0x00
+        </enum>
+        <default>0x01</default>
+        <platInit/>
+        <mssAccessorName>omi_dl_ln_rev_enable</mssAccessorName>
+    </attribute>
+
+     <attribute>
+        <id>ATTR_OMI_DL_X4_BACKOFF_ENABLE</id>
+        <targetType>TARGET_TYPE_OMI</targetType>
+        <description>
+            The DL half width backoff enable bit in DL_CONFIG0_CFG (bit 47)
+        </description>
+        <valueType>uint8</valueType>
+        <enum>
+           ENABLED  = 0x01,
+           DISABLED = 0x00
+        </enum>
+        <default>0x01</default>
+        <platInit/>
+        <mssAccessorName>omi_dl_x4_backoff_enable</mssAccessorName>
+    </attribute>
+
+</attributes>
diff --git a/src/import/chips/p9a/procedures/hwp/memory/lib/mc/omi.H b/src/import/chips/p9a/procedures/hwp/memory/lib/mc/omi.H
index 7bb473659..f7a9f08b3 100644
--- a/src/import/chips/p9a/procedures/hwp/memory/lib/mc/omi.H
+++ b/src/import/chips/p9a/procedures/hwp/memory/lib/mc/omi.H
@@ -48,6 +48,7 @@
 #include <generic/memory/lib/utils/find.H>
 #include <generic/memory/lib/mss_generic_system_attribute_getters.H>
 #include <generic/memory/lib/mss_generic_attribute_getters.H>
+#include <mss_p9a_attribute_getters.H>
 
 namespace mss
 {
@@ -476,6 +477,8 @@ fapi2::ReturnCode setup_mc_config0_helper(const fapi2::Target<T>& i_target)
 {
     // The value is 0x8200040000152824
     fapi2::buffer<uint64_t> l_val;
+    uint8_t l_dl_tx_ln_rev_en = 1;
+    uint8_t l_dl_x4_backoff_en = 1;
 
     // CFG_DL0_ENABLE: dl0 enabled
     l_val.template writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_ENABLE>(1);
@@ -544,7 +547,9 @@ fapi2::ReturnCode setup_mc_config0_helper(const fapi2::Target<T>& i_target)
     l_val.template writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_UNUSED2>(0);
 
     // CFG_DL0_TX_LN_REV_ENA: When set will allow dl0 to perform tx lane reversals.
-    l_val.template writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_TX_LN_REV_ENA>(0);
+    FAPI_TRY(mss::attr::get_omi_dl_ln_rev_enable(i_target, l_dl_tx_ln_rev_en),
+             "Error from FAPI_ATTR_GET (ATTR_OMI_DL_LN_REV_ENABLE)");
+    l_val.template writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_TX_LN_REV_ENA>(l_dl_tx_ln_rev_en);
 
     // CFG_DL0_128_130_ENCODING_ENABLED: dl0 128/130 encoding enabled
     l_val.template writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_128_130_ENCODING_ENABLED>(0);
@@ -562,7 +567,9 @@ fapi2::ReturnCode setup_mc_config0_helper(const fapi2::Target<T>& i_target)
     l_val.template writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_X1_BACKOFF_ENABLE>(0);
 
     // CFG_DL0_HALF_WIDTH_BACKOFF_ENABLE: dl0 x4 backoff enabled
-    l_val.template writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_X4_BACKOFF_ENABLE>(1);
+    FAPI_TRY(mss::attr::get_omi_dl_x4_backoff_enable(i_target, l_dl_x4_backoff_en),
+             "Error from FAPI_ATTR_GET (ATTR_OMI_DL_X4_BACKOFF_ENABLE)");
+    l_val.template writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_X4_BACKOFF_ENABLE>(l_dl_x4_backoff_en);
 
     l_val.template insertFromRight<TT::MC_REG2_DL0_CONFIG0_CFG_SUPPORTED_MODES,
                    TT::MC_REG2_DL0_CONFIG0_CFG_SUPPORTED_MODES_LEN>(LINK_WIDTHS_X8);
diff --git a/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_train.mk b/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_train.mk
index f2deb6d74..83c2d899f 100644
--- a/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_train.mk
+++ b/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_train.mk
@@ -27,5 +27,5 @@
 -include 00p9a_common.mk
 
 PROCEDURE=p9a_omi_train
-$(eval $(call ADD_MEMORY_INCDIRS,$(PROCEDURE)))
+$(eval $(call ADD_P9A_MEMORY_INCDIRS,$(PROCEDURE)))
 $(call BUILD_PROCEDURE)
diff --git a/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_train_check.mk b/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_train_check.mk
index 9f148de86..b976082cb 100644
--- a/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_train_check.mk
+++ b/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_train_check.mk
@@ -27,5 +27,5 @@
 -include 00p9a_common.mk
 
 PROCEDURE=p9a_omi_train_check
-$(eval $(call ADD_MEMORY_INCDIRS,$(PROCEDURE)))
+$(eval $(call ADD_P9A_MEMORY_INCDIRS,$(PROCEDURE)))
 $(call BUILD_PROCEDURE)