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| author | Richard J. Knight <rjknight@us.ibm.com> | 2016-01-14 12:55:42 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-05-13 15:28:06 -0400 |
| commit | 8de9307889001eea0c7f432e68d7b10e079431b2 (patch) | |
| tree | 36edbba5ee40126e9756eb76f93260b5eb932649 /src/import | |
| parent | 51aa72abdd11b62d8040cc60a103bbf3cba0a829 (diff) | |
| download | talos-hostboot-8de9307889001eea0c7f432e68d7b10e079431b2.tar.gz talos-hostboot-8de9307889001eea0c7f432e68d7b10e079431b2.zip | |
Update register names in xml file to match scomdef file.
Change-Id: I7206abf4bd7449ea203e2fc52451a9d5d545ea43
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/23316
Tested-by: Jenkins Server
Reviewed-by: WILLIAM G. HOFFA <wghoffa@us.ibm.com>
Reviewed-by: Brian Silver <bsilver@us.ibm.com>
Reviewed-by: Andre A. Marin <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24467
Tested-by: FSP CI Jenkins
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit_training.xml | 42 |
1 files changed, 21 insertions, 21 deletions
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit_training.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit_training.xml index 16b964e49..a7e7f3394 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit_training.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit_training.xml @@ -7,7 +7,7 @@ <!-- --> <!-- EKB Project --> <!-- --> -<!-- COPYRIGHT 2015 --> +<!-- COPYRIGHT 2015,2016 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -53,26 +53,26 @@ <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_2</scomRegister> <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_3</scomRegister> <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_4</scomRegister> - <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P1_0</scomRegister> - <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P1_1</scomRegister> - <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P1_2</scomRegister> - <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P1_3</scomRegister> - <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P1_4</scomRegister> - <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P1_0</scomRegister> - <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P1_1</scomRegister> - <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P1_2</scomRegister> - <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P1_3</scomRegister> - <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P1_4</scomRegister> - <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P1_0</scomRegister> - <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P1_1</scomRegister> - <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P1_2</scomRegister> - <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P1_3</scomRegister> - <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P1_4</scomRegister> - <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P1_0</scomRegister> - <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P1_1</scomRegister> - <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P1_2</scomRegister> - <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P1_3</scomRegister> - <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P1_4</scomRegister> + <scomRegister>MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P1_0</scomRegister> + <scomRegister>MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P1_1</scomRegister> + <scomRegister>MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P1_2</scomRegister> + <scomRegister>MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P1_3</scomRegister> + <scomRegister>MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P1_4</scomRegister> + <scomRegister>MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P1_0</scomRegister> + <scomRegister>MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P1_1</scomRegister> + <scomRegister>MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P1_2</scomRegister> + <scomRegister>MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P1_3</scomRegister> + <scomRegister>MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P1_4</scomRegister> + <scomRegister>MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P1_0</scomRegister> + <scomRegister>MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P1_1</scomRegister> + <scomRegister>MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P1_2</scomRegister> + <scomRegister>MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P1_3</scomRegister> + <scomRegister>MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P1_4</scomRegister> + <scomRegister>MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P1_0</scomRegister> + <scomRegister>MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P1_1</scomRegister> + <scomRegister>MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P1_2</scomRegister> + <scomRegister>MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P1_3</scomRegister> + <scomRegister>MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P1_4</scomRegister> </registerFfdc> <hwpError> |
