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| author | Yue Du <daviddu@us.ibm.com> | 2016-10-24 10:59:37 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-11-14 10:21:19 -0500 |
| commit | 79365796a27a6de1d7b55cd41201480b3dd45194 (patch) | |
| tree | f142a18e899e911a933c0061579b803e8ebfc0c0 /src/import | |
| parent | 896e334b6bd5002c890fe0e2aebba505316af5ef (diff) | |
| download | talos-hostboot-79365796a27a6de1d7b55cd41201480b3dd45194.tar.gz talos-hostboot-79365796a27a6de1d7b55cd41201480b3dd45194.zip | |
Istep4: Enable poll for DPLL lock in p9_hcd_cache_dpll_setup
changes in this commit:
1) enable dpll lock checking in non-sim envrionment
2) change FAPI_DBG lines on set/reset sdis_n ops as
removing prints saying they are DD1 only workaround
due to they are permenant steps now
3) add missing content of p9_hcd_core_dcc_skewadjust
4) add DD2 sram_enable support (NOOP for DD1)
Change-Id: I74fc3b05781e7cd13bb8c95b0dc7389029d7c5af
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31719
Reviewed-by: Joseph E. Dery <dery@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: CHRISTOPHER M. RIEDL <cmriedl@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31811
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C | 13 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml | 18 |
2 files changed, 28 insertions, 3 deletions
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C index 2bec05ee7..85b92b545 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C @@ -75,9 +75,14 @@ p9_hcd_core_stopclocks( uint32_t l_loops1ms; uint8_t l_attr_chip_unit_pos; uint8_t l_attr_vdm_enable; + uint8_t l_attr_sdisn_setup; const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> l_sys; auto l_quad = i_target.getParent<fapi2::TARGET_TYPE_EQ>(); auto l_perv = i_target.getParent<fapi2::TARGET_TYPE_PERV>(); + auto l_chip = i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>(); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_SDISN_SETUP, l_chip, + l_attr_sdisn_setup)); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_VDM_ENABLE, l_sys, l_attr_vdm_enable)); @@ -221,9 +226,11 @@ p9_hcd_core_stopclocks( FAPI_DBG("Assert regional fences via CPLT_CTRL1[4-14]"); FAPI_TRY(putScom(i_target, C_CPLT_CTRL1_OR, p9hcd::CLK_REGION_ALL)); - /// @todo RTC158181 add DD1 attribute control - FAPI_DBG("DD1 only: reset sdis_n(flushing LCBES condition workaround"); - FAPI_TRY(putScom(i_target, C_CPLT_CONF0_CLEAR, MASK_SET(34))); + if (l_attr_sdisn_setup) + { + FAPI_DBG("DD1 Only: Drop sdis_n(flushing LCBES condition) vai CPLT_CONF0[34]"); + FAPI_TRY(putScom(i_target, C_CPLT_CONF0_CLEAR, MASK_SET(34))); + } // ------------------------------- // Disable VDM diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index d1d0e868b..594471c61 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -183,6 +183,24 @@ </attribute> <!-- ******************************************************************** --> <attribute> + <id>ATTR_CHIP_EC_FEATURE_SDISN_SETUP</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Sdis_n set or clear : flushing LCBES condition woraround. True if: + Nimbus EC less than 20 + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x20</value> + <test>LESS_THAN</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> + <attribute> <id>ATTR_CHIP_EC_FEATURE_HW388878</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> |
