diff options
author | spashabk-in <shakeebbk@in.ibm.com> | 2016-12-23 01:28:27 -0600 |
---|---|---|
committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-05-24 22:35:59 -0400 |
commit | 7738208e04ad42fd8f9e5d4e3e51d8f27eb4c95f (patch) | |
tree | 5d8221958e4ae0399a0bbfec78a6bcb0ba511cfe /src/import | |
parent | 8cb9e23b499f04e65cd71b1d3e78b3f2763c1159 (diff) | |
download | talos-hostboot-7738208e04ad42fd8f9e5d4e3e51d8f27eb4c95f.tar.gz talos-hostboot-7738208e04ad42fd8f9e5d4e3e51d8f27eb4c95f.zip |
Tracearray HWP L2
Change-Id: I2fbb02f8dc372f37aa725e26fb5ee2dd307ac275
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34191
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40875
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import')
5 files changed, 186 insertions, 364 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_proc_gettracearray.C b/src/import/chips/p9/procedures/hwp/perv/p9_proc_gettracearray.C index df37d6dd9..9af6a2a27 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_proc_gettracearray.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_proc_gettracearray.C @@ -41,7 +41,7 @@ //------------------------------------------------------------------------------ // *HWP HW Owner : Joachim Fenkes <fenkes@de.ibm.com> // *HWP HW Backup Owner : Joe McGill <jmcgill@us.ibm.com> -// *HWP FW Owner : Thi Tran <thi@us.ibm.com> +// *HWP FW Owner : Shakeeb Pasha <shakeebbk@in.ibm.com> // *HWP Team : Perv // *HWP Level : 2 // *HWP Consumed by : FSP @@ -52,141 +52,6 @@ //------------------------------------------------------------------------------ #include "p9_proc_gettracearray.H" -#include <p9_mc_scom_addresses.H> -#include <p9_misc_scom_addresses.H> -#include <p9_obus_scom_addresses.H> -#include <p9_perv_scom_addresses.H> -#include <p9_perv_scom_addresses_fld.H> -#include <p9_quad_scom_addresses.H> -#include <p9_xbus_scom_addresses.H> - -//------------------------------------------------------------------------------ -// Constant definitions -//------------------------------------------------------------------------------ - -// offset to store high/low data within a given entry -const uint32_t HI_BIT_OFFSET = 0; -const uint32_t LO_BIT_OFFSET = 64; - -const uint32_t DEBUG_TRACE_CONTROL_OFS = PERV_DEBUG_TRACE_CONTROL - PERV_DBG_MODE_REG; - -const uint32_t DEBUG_TRACE_CONTROL_START = 0; -const uint32_t DEBUG_TRACE_CONTROL_STOP = 1; -const uint32_t DEBUG_TRACE_CONTROL_RESET = 2; - -const uint32_t TRACE_HI_DATA_OFS = - PERV_TP_TPCHIP_TRA0_TR0_TRACE_HI_DATA_REG - PERV_TP_TPCHIP_TRA0_TR0_TRACE_HI_DATA_REG; -const uint32_t TRACE_LO_DATA_OFS = - PERV_TP_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG - PERV_TP_TPCHIP_TRA0_TR0_TRACE_HI_DATA_REG; -const uint32_t TRACE_TRCTRL_CONFIG_OFS = - PERV_TP_TPCHIP_TRA0_TR0_TRACE_TRCTRL_CONFIG - PERV_TP_TPCHIP_TRA0_TR0_TRACE_HI_DATA_REG; - -const uint32_t EX_L21_SCOM_OFFSET = EQ_TPLC21_TR0_TRACE_HI_DATA_REG - EQ_TPLC20_TR0_TRACE_HI_DATA_REG; -const uint32_t EX_L31_SCOM_OFFSET = EQ_L3TRA1_TR0_TRACE_HI_DATA_REG - EQ_L3TRA0_TR0_TRACE_HI_DATA_REG; - -const uint32_t TRACE_LO_DATA_RUNNING = PERV_1_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG_RUNNING; -const uint32_t TRCTRL_MUX0_SEL = 14; -const uint32_t TRCTRL_MUX0_SEL_LEN = 2; - -const uint32_t TRACE_MUX_POSITIONS = 1 << TRCTRL_MUX0_SEL_LEN; - -//------------------------------------------------------------------------------ -// Table of known trace arrays -//------------------------------------------------------------------------------ - -struct ta_def -{ - /* One entry per mux setting; value of 0 means N/A */ - p9_tracearray_bus_id bus_ids[TRACE_MUX_POSITIONS]; - uint32_t debug_scom_base, trace_scom_base, ex_odd_scom_offset; -}; - -p9_tracearray_bus_id NO_TB = (p9_tracearray_bus_id)0; - -static const ta_def ta_defs[] = -{ - /* PERV */ - { { PROC_TB_PIB, PROC_TB_OCC, PROC_TB_TOD }, PERV_TP_DBG_MODE_REG, PERV_TP_TPCHIP_TRA0_TR0_TRACE_HI_DATA_REG }, - { { PROC_TB_SBE, PROC_TB_PIB_ALT }, PERV_TP_DBG_MODE_REG, PERV_TP_TPCHIP_TRA0_TR1_TRACE_HI_DATA_REG }, - /* N0 */ - { { PROC_TB_PBIOE0 }, PU_N0_DBG_MODE_REG, PU_TCN0_TRA0_TR0_TRACE_HI_DATA_REG }, - { { PROC_TB_PBIOE1 }, PU_N0_DBG_MODE_REG, PU_TCN0_TRA0_TR1_TRACE_HI_DATA_REG }, - { { PROC_TB_CXA0, PROC_TB_NX }, PU_N0_DBG_MODE_REG, PU_TCN0_TRA1_TR0_TRACE_HI_DATA_REG }, - /* N1 */ - { { PROC_TB_PB6 }, PU_N1_DBG_MODE_REG, PU_TCN1_TRA0_TR0_TRACE_HI_DATA_REG }, - { { PROC_TB_PB7 }, PU_N1_DBG_MODE_REG, PU_TCN1_TRA0_TR1_TRACE_HI_DATA_REG }, - { { PROC_TB_PB8 }, PU_N1_DBG_MODE_REG, PU_TCN1_TRA1_TR0_TRACE_HI_DATA_REG }, - { { PROC_TB_PB9 }, PU_N1_DBG_MODE_REG, PU_TCN1_TRA1_TR1_TRACE_HI_DATA_REG }, - { { PROC_TB_PB10 }, PU_N1_DBG_MODE_REG, PU_TCN1_TRA2_TR0_TRACE_HI_DATA_REG }, - { { PROC_TB_PB11 }, PU_N1_DBG_MODE_REG, PU_TCN1_TRA2_TR1_TRACE_HI_DATA_REG }, - { { PROC_TB_MCD0, PROC_TB_MCD1, PROC_TB_VAS }, PU_N1_DBG_MODE_REG, PU_TCN1_TRA3_TR0_TRACE_HI_DATA_REG }, - { { PROC_TB_MCS2, PROC_TB_MCS3, PROC_TB_PB13 }, PU_N1_DBG_MODE_REG, PU_TCN1_TRA3_TR1_TRACE_HI_DATA_REG }, - { { PROC_TB_PBIO0 }, PU_N1_DBG_MODE_REG, PU_TCN1_TRA4_TR0_TRACE_HI_DATA_REG }, - { { PROC_TB_PBIO1 }, PU_N1_DBG_MODE_REG, PU_TCN1_TRA4_TR1_TRACE_HI_DATA_REG }, - /* N2 */ - { { PROC_TB_CXA1, PROC_TB_IOPSI }, PU_N2_DBG_MODE_REG, PU_TCN2_TRA0_TR0_TRACE_HI_DATA_REG }, - { { PROC_TB_PCIS0, PROC_TB_PCIS1, PROC_TB_PCIS2 }, PU_N2_DBG_MODE_REG, PU_TCN2_TRA0_TR1_TRACE_HI_DATA_REG }, - /* N3 */ - { { PROC_TB_PB0 }, PU_N3_DBG_MODE_REG, PU_TCN3_TRA0_TR0_TRACE_HI_DATA_REG }, - { { PROC_TB_PB1 }, PU_N3_DBG_MODE_REG, PU_TCN3_TRA0_TR1_TRACE_HI_DATA_REG }, - { { PROC_TB_PB2 }, PU_N3_DBG_MODE_REG, PU_TCN3_TRA1_TR0_TRACE_HI_DATA_REG }, - { { PROC_TB_PB3 }, PU_N3_DBG_MODE_REG, PU_TCN3_TRA1_TR1_TRACE_HI_DATA_REG }, - { { PROC_TB_PB4 }, PU_N3_DBG_MODE_REG, PU_TCN3_TRA2_TR0_TRACE_HI_DATA_REG }, - { { PROC_TB_PB5 }, PU_N3_DBG_MODE_REG, PU_TCN3_TRA2_TR1_TRACE_HI_DATA_REG }, - { { PROC_TB_INT, PROC_TB_NPU1, PROC_TB_NMMU1 }, PU_N3_DBG_MODE_REG, PU_TCN3_TRA3_TR0_TRACE_HI_DATA_REG }, - { { PROC_TB_MCS0, PROC_TB_MCS1, PROC_TB_PB12 }, PU_N3_DBG_MODE_REG, PU_TCN3_TRA3_TR1_TRACE_HI_DATA_REG }, - { { PROC_TB_BRIDGE }, PU_N3_DBG_MODE_REG, PU_TCN3_TRA4_TR0_TRACE_HI_DATA_REG }, - { { PROC_TB_NPU0 }, PU_N3_DBG_MODE_REG, PU_TCN3_TRA5_TR0_TRACE_HI_DATA_REG }, - { { PROC_TB_NMMU0 }, PU_N3_DBG_MODE_REG, PU_TCN3_TRA5_TR1_TRACE_HI_DATA_REG }, - /* XBUS */ - { { PROC_TB_PBIOX0, PROC_TB_IOX0 }, XBUS_PERV_DBG_MODE_REG, XBUS_PERV_TCXB_TRA0_TR0_TRACE_HI_DATA_REG }, - { { PROC_TB_PBIOX1, PROC_TB_IOX1 }, XBUS_PERV_DBG_MODE_REG, XBUS_PERV_TCXB_TRA0_TR1_TRACE_HI_DATA_REG }, - { { PROC_TB_PBIOX2, PROC_TB_IOX2 }, XBUS_PERV_DBG_MODE_REG, XBUS_PERV_TCXB_TRA1_TR0_TRACE_HI_DATA_REG }, - /* PCIx */ - { { PROC_TB_PCI0X, PROC_TB_PCI00 }, PEC_0_DBG_MODE_REG, PEC_0_TCPCI0_TRA0_TR0_TRACE_HI_DATA_REG }, - { { PROC_TB_PCI1X, PROC_TB_PCI11, PROC_TB_PCI12 }, PEC_1_DBG_MODE_REG, PEC_1_TCPCI1_TRA0_TR0_TRACE_HI_DATA_REG }, - { { PROC_TB_PCI2X, PROC_TB_PCI23, PROC_TB_PCI24, PROC_TB_PCI25 }, PEC_2_DBG_MODE_REG, PEC_2_TCPCI2_TRA0_TR0_TRACE_HI_DATA_REG }, - /* OBUS */ - { { PROC_TB_PBIOOA, PROC_TB_IOO }, OBUS_TCOB0_DBG_MODE_REG, OBUS_TCOB0_TRA0_TR0_TRACE_HI_DATA_REG }, - /* MC */ - { { PROC_TB_MCA0 }, MCA_3_DBG_MODE_REG, PU_TCMC01_FAST_TRA0_TRACE_HI_DATA_REG }, - { { PROC_TB_MCA1 }, MCA_3_DBG_MODE_REG, PU_TCMC01_FAST_TRA1_TRACE_HI_DATA_REG }, - { { PROC_TB_IOMC0, PROC_TB_IOMC1, PROC_TB_IOMC2, PROC_TB_IOMC3 }, MCA_3_DBG_MODE_REG, MCA_TCMC01_SLOW_TRA0_TRACE_HI_DATA_REG }, - /* EX */ - { { PROC_TB_L20, NO_TB, NO_TB, PROC_TB_SKIT10 }, EQ_DBG_MODE_REG, EQ_TPLC20_TR0_TRACE_HI_DATA_REG, EX_L21_SCOM_OFFSET }, - { { PROC_TB_L21, NO_TB, NO_TB, PROC_TB_SKIT11 }, EQ_DBG_MODE_REG, EQ_TPLC20_TR1_TRACE_HI_DATA_REG, EX_L21_SCOM_OFFSET }, - { { PROC_TB_L30, PROC_TB_NCU0, PROC_TB_CME, PROC_TB_EQPB }, EQ_DBG_MODE_REG, EQ_L3TRA0_TR0_TRACE_HI_DATA_REG, EX_L31_SCOM_OFFSET }, - { { PROC_TB_L31, PROC_TB_NCU1, PROC_TB_IVRM, PROC_TB_SKEWADJ }, EQ_DBG_MODE_REG, EQ_L3TRA0_TR1_TRACE_HI_DATA_REG, EX_L31_SCOM_OFFSET }, - /* CORE */ - { { PROC_TB_CORE0 }, C_DBG_MODE_REG, 0x00011440 }, - { { PROC_TB_CORE1 }, C_DBG_MODE_REG, 0x00011480 }, -}; - -#define ARRAY_SIZE(array) (sizeof(array) / sizeof(array[0])) - -class TraceArrayFinder -{ - public: - const ta_def* pdef; - uint32_t mux_sel; - - TraceArrayFinder(p9_tracearray_bus_id i_trace_bus) : pdef(NULL), mux_sel(0) - { - for (unsigned int i = 0; i < ARRAY_SIZE(ta_defs); i++) - { - for (uint32_t sel = 0; sel < TRACE_MUX_POSITIONS; sel++) - { - if (ta_defs[i].bus_ids[sel] == i_trace_bus) - { - pdef = ta_defs + i; - mux_sel = sel; - return; - } - } - } - } -}; - //------------------------------------------------------------------------------ // HWP entry point //------------------------------------------------------------------------------ @@ -195,137 +60,46 @@ extern "C" fapi2::ReturnCode p9_proc_gettracearray( const proc_gettracearray_args& i_args, fapi2::variable_buffer& o_ta_data) { - fapi2::Target < PROC_GETTRACEARRAY_TARGET_TYPES | fapi2::TARGET_TYPE_EQ > target = i_target; - uint32_t tra_scom_offset = 0; + fapi2::ReturnCode l_fapiRc = fapi2::FAPI2_RC_SUCCESS; // mark HWP entry - FAPI_IMP("Entering ..."); + FAPI_INF("Entering ..."); - const TraceArrayFinder l_ta_finder(i_args.trace_bus); + fapi2::Target<P9_SBE_TRACEARRAY_TARGET_TYPES> l_target; + const uint8_t l_chiplet_num = i_target.getChipletNumber(); - if (!l_ta_finder.pdef) + if(IS_MCBIST(l_chiplet_num) || IS_OBUS(l_chiplet_num)) { - FAPI_ERR("Unsupported trace bus identifier %d specified", i_args.trace_bus); - return fapi2::RC_PROC_GETTRACEARRAY_INVALID_BUS; - ; + l_target = i_target.getParent<fapi2::TARGET_TYPE_PERV>(); } - - const uint32_t DEBUG_TRACE_CONTROL = l_ta_finder.pdef->debug_scom_base + DEBUG_TRACE_CONTROL_OFS; - const uint32_t TRACE_SCOM_BASE = l_ta_finder.pdef->trace_scom_base; - - fapi2::TargetType arg_type = i_target.getType(); - fapi2::TargetType ta_type = proc_gettracearray_target_type(i_args.trace_bus); - - if ((arg_type & ta_type) == 0) - { - FAPI_ERR("Specified trace array requires target type 0x%X, but the supplied target is of type 0x%X", ta_type, arg_type); - return fapi2::RC_PROC_GETTRACEARRAY_INVALID_TARGET; - } - - /* Nimbus DD1 core traces can't be read out via SCOM. Check an EC feature to see if that's fixed. */ - if (ta_type == fapi2::TARGET_TYPE_CORE) - { - uint8_t l_core_trace_scomable = 0; - - fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> proc_target = i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>(); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_CORE_TRACE_SCOMABLE, proc_target, l_core_trace_scomable), - "Failed to query chip EC feature ATTR_CHIP_EC_FEATURE_CORE_TRACE_SCOMABLE"); - - if (!l_core_trace_scomable) - { - FAPI_ERR("Core arrays cannot be dumped in this chip EC; please use fastarray instead."); - return fapi2::RC_PROC_GETTRACEARRAY_CORE_NOT_DUMPABLE; - } - } - - /* For convenience, we link Cache trace arrays to the virtual EX chiplets. Transform back - * to EQ chiplet and SCOM address offset. */ - if (ta_type == fapi2::TARGET_TYPE_EX) - { - uint8_t l_chipunit_num; - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target, l_chipunit_num), - "Failed to get chipUnit ID from EX target"); - target = i_target.getParent<fapi2::TARGET_TYPE_EQ>(); - - if (l_chipunit_num & 1) - { - tra_scom_offset = l_ta_finder.pdef->ex_odd_scom_offset; - } - } - - /* Check that the trace mux is set up as expected */ - if (!i_args.ignore_mux_setting) - { - fapi2::buffer<uint64_t> buf; - FAPI_TRY(fapi2::getScom(target, TRACE_SCOM_BASE + tra_scom_offset + TRACE_TRCTRL_CONFIG_OFS, buf), - "Failed to read current trace mux setting"); - uint32_t cur_sel = 0; - buf.extractToRight<TRCTRL_MUX0_SEL, TRCTRL_MUX0_SEL_LEN>(cur_sel); - - if (cur_sel != l_ta_finder.mux_sel) - { - FAPI_ERR("Primary trace mux is set to %d, but %d is needed for requested trace bus", cur_sel, l_ta_finder.mux_sel); - return fapi2::RC_PROC_GETTRACEARRAY_TRACE_MUX_INCORRECT; - } - } - - if (i_args.stop_pre_dump) + else { - FAPI_DBG("Stopping trace arrays"); - fapi2::buffer<uint64_t> buf; - buf.flush<0>().setBit<DEBUG_TRACE_CONTROL_STOP>(); - FAPI_TRY(fapi2::putScom(target, DEBUG_TRACE_CONTROL, buf), "Failed to stop chiplet domain trace arrays"); + l_target = i_target.get(); } - if (i_args.collect_dump) - { - fapi2::buffer<uint64_t> buf; - o_ta_data.resize(P9_TRACEARRAY_NUM_ROWS * P9_TRACEARRAY_BITS_PER_ROW).flush<0>(); - - /* Start with the low data register because that's where the "trace running" bit is. */ - for (int i = 0; i < P9_TRACEARRAY_NUM_ROWS; i++) - { - FAPI_TRY(fapi2::getScom(target, TRACE_SCOM_BASE + tra_scom_offset + TRACE_LO_DATA_OFS, buf), - "Failed to read trace array low data register, iteration %d", i); - - /* The "trace running" bit is our best indicator of whether the array is currently running. - * If it is, the read won't have incremented the address, so it's okay to bail out. */ - if (buf.getBit<TRACE_LO_DATA_RUNNING>()) - { - FAPI_ERR("Trace array is still running -- If you think you stopped it, maybe the controlling debug macro is slaved to another debug macro?"); - return fapi2::RC_PROC_GETTRACEARRAY_TRACE_RUNNING; - } - - FAPI_TRY(o_ta_data.set<uint64_t>(buf, 2 * i + 1), "Failed to insert data into trace buffer"); - } + o_ta_data.resize(P9_TRACEARRAY_NUM_ROWS * P9_TRACEARRAY_BITS_PER_ROW).flush<0>(); + uint64_t l_data_buffer[P9_TRACEARRAY_NUM_ROWS * P9_TRACEARRAY_BITS_PER_ROW / 8 / sizeof(uint64_t)] = {}; - /* Then dump the high data */ - for (int i = 0; i < P9_TRACEARRAY_NUM_ROWS; i++) - { - FAPI_TRY(fapi2::getScom(target, TRACE_SCOM_BASE + tra_scom_offset + TRACE_HI_DATA_OFS, buf), - "Failed to read trace array high data register, iteration %d", i); - FAPI_TRY(o_ta_data.set<uint64_t>(buf, 2 * i + 0), "Failed to insert data into trace buffer"); - } - } + l_fapiRc = p9_sbe_tracearray( + l_target, + i_args, + l_data_buffer, + 0, + P9_TRACEARRAY_NUM_ROWS); + FAPI_TRY(l_fapiRc, + "p9_sbe_tracearray failed"); - if (i_args.reset_post_dump) + for(uint32_t i = 0; i < P9_TRACEARRAY_NUM_ROWS; i++) { - FAPI_DBG("Resetting trace arrays"); - fapi2::buffer<uint64_t> buf; - buf.flush<0>().setBit<DEBUG_TRACE_CONTROL_RESET>(); - FAPI_TRY(fapi2::putScom(target, DEBUG_TRACE_CONTROL, buf), "Failed to reset chiplet domain trace arrays"); + FAPI_TRY(o_ta_data.set<uint64_t>(l_data_buffer[2 * i + 0], 2 * i + 0), + "Failed to insert data into trace buffer"); + FAPI_TRY(o_ta_data.set<uint64_t>(l_data_buffer[2 * i + 1], 2 * i + 1), + "Failed to insert data into trace buffer"); } - if (i_args.restart_post_dump) - { - FAPI_DBG("Starting trace arrays"); - fapi2::buffer<uint64_t> buf; - buf.flush<0>().setBit<DEBUG_TRACE_CONTROL_START>(); - FAPI_TRY(fapi2::putScom(target, DEBUG_TRACE_CONTROL, buf), "Failed to restart chiplet domain trace arrays"); - } // mark HWP exit - FAPI_IMP("Success"); + FAPI_INF("Success"); return fapi2::FAPI2_RC_SUCCESS; fapi_try_exit: diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_proc_gettracearray.H b/src/import/chips/p9/procedures/hwp/perv/p9_proc_gettracearray.H index a47139231..d579ed5ec 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_proc_gettracearray.H +++ b/src/import/chips/p9/procedures/hwp/perv/p9_proc_gettracearray.H @@ -41,7 +41,7 @@ //------------------------------------------------------------------------------ // *HWP HW Owner : Joachim Fenkes <fenkes@de.ibm.com> // *HWP HW Backup Owner : Joe McGill <jmcgill@us.ibm.com> -// *HWP FW Owner : Thi Tran <thi@us.ibm.com> +// *HWP FW Owner : Shakeeb Pasha <shakeebbk@in.ibm.com> // *HWP Team : Perv // *HWP Level : 2 // *HWP Consumed by : FSP @@ -57,6 +57,8 @@ #include <fapi2.H> #include "p9_tracearray_defs.H" +#include "p9_sbe_tracearray.H" + static const fapi2::TargetType PROC_GETTRACEARRAY_TARGET_TYPES = fapi2::TARGET_TYPE_PROC_CHIP | fapi2::TARGET_TYPE_OBUS | @@ -64,17 +66,6 @@ static const fapi2::TargetType PROC_GETTRACEARRAY_TARGET_TYPES = fapi2::TARGET_TYPE_EX | fapi2::TARGET_TYPE_CORE; -// structure to represent HWP arguments -struct proc_gettracearray_args -{ - p9_tracearray_bus_id trace_bus; ///< The trace bus whose associated trace array should be dumped - bool stop_pre_dump; ///< Stop the trace array before starting the dump - bool ignore_mux_setting; ///< Do not fail if the primary trace mux is set to a different bus - bool collect_dump; ///< Do dump the trace array; useful if you just want to start/stop - bool reset_post_dump; ///< Reset the debug logic after dumping - bool restart_post_dump; ///< Start the trace array after dumping -}; - // function pointer typedef definition for HWP call support typedef fapi2::ReturnCode (*p9_proc_gettracearray_FP_t)(const fapi2::Target<PROC_GETTRACEARRAY_TARGET_TYPES>&, diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_proc_gettracearray.mk b/src/import/chips/p9/procedures/hwp/perv/p9_proc_gettracearray.mk index 86196122f..a0c83872c 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_proc_gettracearray.mk +++ b/src/import/chips/p9/procedures/hwp/perv/p9_proc_gettracearray.mk @@ -23,4 +23,6 @@ # # IBM_PROLOG_END_TAG PROCEDURE=p9_proc_gettracearray +OBJS += p9_sbe_tracearray.o $(call BUILD_PROCEDURE) + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tracearray.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tracearray.C index a2f1ef164..f6cb436e6 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tracearray.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tracearray.C @@ -43,7 +43,7 @@ // *HWP FW Owner : Shakeeb Pasha<shakeebbk@in.ibm.com> // *HWP Team : Perv // *HWP Level : 1 -// *HWP Consumed by : SBE +// *HWP Consumed by : Cronus, SBE //------------------------------------------------------------------------------ //----------------------------------------------------------------------------------- // Includes @@ -91,7 +91,6 @@ const uint32_t TRCTRL_MUX0_SEL_LEN = 2; const uint32_t TRACE_MUX_POSITIONS = 1 << TRCTRL_MUX0_SEL_LEN; const uint32_t TA_BASE_SCOM_MULTIPLIER = 0x00000040; -const uint32_t TA_EX_OFFSET_MULTIPLIER = 0x00000040; const uint32_t TA_DEBUG_BASE_SCOM = 0x000107C0; const uint32_t TA_TRACE_BASE_SCOM = 0x00010400; //------------------------------------------------------------------------------ @@ -102,72 +101,70 @@ struct ta_def { /* One entry per mux setting; value of 0 means N/A */ p9_tracearray_bus_id bus_ids[TRACE_MUX_POSITIONS]; - const uint8_t chiplet; - const uint8_t base_multiplier; - const uint8_t ex_multiplier; -}; + const uint8_t ex_odd_scom_offset: 2; + const uint8_t chiplet: 6; + const uint8_t base_multiplier; + }; -static const ta_def ta_defs[] = + static const ta_def ta_defs[] = { /* PERV */ - { { PROC_TB_PIB, PROC_TB_OCC, PROC_TB_TOD }, 0x01, 0x00, 0x00}, - { { PROC_TB_SBE, PROC_TB_PIB_ALT }, 0x01, 0x01, 0x00}, + { { PROC_TB_PIB, PROC_TB_OCC, PROC_TB_TOD }, 0x00, 0x01, 0x00}, + { { PROC_TB_SBE, PROC_TB_PIB_ALT }, 0x00, 0x01, 0x01}, /* N0 */ - { { PROC_TB_PBIOE0 }, 0x02, 0x00, 0x00}, - { { PROC_TB_PBIOE1 }, 0x02, 0x01, 0x00}, - { { PROC_TB_CXA0, PROC_TB_NX }, 0x02, 0x02, 0x00}, + { { PROC_TB_PBIOE0 }, 0x00, 0x02, 0x00}, + { { PROC_TB_PBIOE1 }, 0x00, 0x02, 0x01}, + { { PROC_TB_CXA0, PROC_TB_NX }, 0x00, 0x02, 0x02}, /* N1 */ - { { PROC_TB_PB6 }, 0x03, 0x00, 0x00}, - { { PROC_TB_PB7 }, 0x03, 0x01, 0x00}, - { { PROC_TB_PB8 }, 0x03, 0x02, 0x00}, - { { PROC_TB_PB9 }, 0x03, 0x03, 0x00}, - { { PROC_TB_PB10 }, 0x03, 0x04, 0x00}, - { { PROC_TB_PB11 }, 0x03, 0x05, 0x00}, - { { PROC_TB_MCD0, PROC_TB_MCD1, PROC_TB_VAS }, 0x03, 0x06, 0x00}, - { { PROC_TB_MCS2, PROC_TB_MCS3, PROC_TB_PB13 }, 0x03, 0x07, 0x00}, - { { PROC_TB_PBIO0 }, 0x03, 0x08, 0x00}, - { { PROC_TB_PBIO1 }, 0x03, 0x09, 0x00}, + { { PROC_TB_PB6 }, 0x00, 0x03, 0x00}, + { { PROC_TB_PB7 }, 0x00, 0x03, 0x01}, + { { PROC_TB_PB8 }, 0x00, 0x03, 0x02}, + { { PROC_TB_PB9 }, 0x00, 0x03, 0x03}, + { { PROC_TB_PB10 }, 0x00, 0x03, 0x04}, + { { PROC_TB_PB11 }, 0x00, 0x03, 0x05}, + { { PROC_TB_MCD0, PROC_TB_MCD1, PROC_TB_VAS }, 0x00, 0x03, 0x06}, + { { PROC_TB_MCS2, PROC_TB_MCS3, PROC_TB_PB13 }, 0x00, 0x03, 0x07}, + { { PROC_TB_PBIO0 }, 0x00, 0x03, 0x08}, + { { PROC_TB_PBIO1 }, 0x00, 0x03, 0x09}, /* N2 */ - { { PROC_TB_CXA1, PROC_TB_IOPSI }, 0x04, 0x00, 0x00}, - { { PROC_TB_PCIS0, PROC_TB_PCIS1, PROC_TB_PCIS2 }, 0x04, 0x01, 0x00}, + { { PROC_TB_CXA1, PROC_TB_IOPSI }, 0x00, 0x04, 0x00}, + { { PROC_TB_PCIS0, PROC_TB_PCIS1, PROC_TB_PCIS2 }, 0x00, 0x04, 0x01}, /* N3 */ - { { PROC_TB_PB0 }, 0x05, 0x00, 0x00}, - { { PROC_TB_PB1 }, 0x05, 0x01, 0x00}, - { { PROC_TB_PB2 }, 0x05, 0x02, 0x00}, - { { PROC_TB_PB3 }, 0x05, 0x03, 0x00}, - { { PROC_TB_PB4 }, 0x05, 0x04, 0x00}, - { { PROC_TB_PB5 }, 0x05, 0x05, 0x00}, - { { PROC_TB_INT, PROC_TB_NPU1, PROC_TB_NMMU1 }, 0x05, 0x06, 0x00}, - { { PROC_TB_MCS0, PROC_TB_MCS1, PROC_TB_PB12 }, 0x05, 0x07, 0x00}, - { { PROC_TB_BRIDGE }, 0x05, 0x08, 0x00}, - { { PROC_TB_NPU0 }, 0x05, 0x0A, 0x00}, - { { PROC_TB_NMMU0 }, 0x05, 0x0B, 0x00}, + { { PROC_TB_PB0 }, 0x00, 0x05, 0x00}, + { { PROC_TB_PB1 }, 0x00, 0x05, 0x01}, + { { PROC_TB_PB2 }, 0x00, 0x05, 0x02}, + { { PROC_TB_PB3 }, 0x00, 0x05, 0x03}, + { { PROC_TB_PB4 }, 0x00, 0x05, 0x04}, + { { PROC_TB_PB5 }, 0x00, 0x05, 0x05}, + { { PROC_TB_INT, PROC_TB_NPU1, PROC_TB_NMMU1 }, 0x00, 0x05, 0x06}, + { { PROC_TB_MCS0, PROC_TB_MCS1, PROC_TB_PB12 }, 0x00, 0x05, 0x07}, + { { PROC_TB_BRIDGE }, 0x00, 0x05, 0x08}, + { { PROC_TB_NPU0 }, 0x00, 0x05, 0x0A}, + { { PROC_TB_NMMU0 }, 0x00, 0x05, 0x0B}, /* XBUS */ - { { PROC_TB_PBIOX0, PROC_TB_IOX0 }, 0x06, 0x00, 0x00}, - { { PROC_TB_PBIOX1, PROC_TB_IOX1 }, 0x06, 0x01, 0x00}, - { { PROC_TB_PBIOX2, PROC_TB_IOX2 }, 0x06, 0x03, 0x00}, + { { PROC_TB_PBIOX0, PROC_TB_IOX0 }, 0x00, 0x06, 0x00}, + { { PROC_TB_PBIOX1, PROC_TB_IOX1 }, 0x00, 0x06, 0x01}, + { { PROC_TB_PBIOX2, PROC_TB_IOX2 }, 0x00, 0x06, 0x02}, /* PCIx */ - { { PROC_TB_PCI0X, PROC_TB_PCI00 }, 0x0D, 0x00, 0x00}, - { { PROC_TB_PCI1X, PROC_TB_PCI11, PROC_TB_PCI12 }, 0x0E, 0x00, 0x00}, - { { PROC_TB_PCI2X, PROC_TB_PCI23, PROC_TB_PCI24, PROC_TB_PCI25 }, 0x0F, 0x00, 0x00}, + { { PROC_TB_PCI0X, PROC_TB_PCI00 }, 0x00, 0x0D, 0x00}, + { { PROC_TB_PCI1X, PROC_TB_PCI11, PROC_TB_PCI12 }, 0x00, 0x0E, 0x00}, + { { PROC_TB_PCI2X, PROC_TB_PCI23, PROC_TB_PCI24, PROC_TB_PCI25 }, 0x00, 0x0F, 0x00}, /* OBUS */ - { { PROC_TB_PBIOOA, PROC_TB_IOO }, 0x09, 0x00, 0x00}, + { { PROC_TB_PBIOOA, PROC_TB_IOO }, 0x00, 0x09, 0x00}, /* MC */ - { { PROC_TB_MCA0 }, 0x07, 0x20, 0x00}, - { { PROC_TB_MCA1 }, 0x07, 0x21, 0x00}, - { { PROC_TB_IOMC0, PROC_TB_IOMC1, PROC_TB_IOMC2, PROC_TB_IOMC3 }, 0x07, 0x00, 0x00}, + { { PROC_TB_MCA0 }, 0x00, 0x07, 0x20}, + { { PROC_TB_MCA1 }, 0x00, 0x07, 0x21}, + { { PROC_TB_IOMC0, PROC_TB_IOMC1, PROC_TB_IOMC2, PROC_TB_IOMC3 }, 0x00, 0x07, 0x00}, /* EX */ - { { PROC_TB_L20, NO_TB, NO_TB, PROC_TB_SKIT10 }, 0x10, 0x94, 0x0C}, - { { PROC_TB_L21, NO_TB, NO_TB, PROC_TB_SKIT11 }, 0x10, 0x95, 0x0C}, - { { PROC_TB_L30, PROC_TB_NCU0, PROC_TB_CME, PROC_TB_EQPB }, 0x10, 0x00, 0x02}, - { { PROC_TB_L31, PROC_TB_NCU1, PROC_TB_IVRM, PROC_TB_SKEWADJ }, 0x10, 0x01, 0x02}, + { { PROC_TB_L20, NO_TB, NO_TB, PROC_TB_SKIT10 }, 0x01, 0x10, 0x94}, + { { PROC_TB_L21, NO_TB, NO_TB, PROC_TB_SKIT11 }, 0x01, 0x10, 0x95}, + { { PROC_TB_L30, PROC_TB_NCU0, PROC_TB_CME, PROC_TB_EQPB }, 0x02, 0x10, 0x00}, + { { PROC_TB_L31, PROC_TB_NCU1, PROC_TB_IVRM, PROC_TB_SKEWADJ }, 0x02, 0x10, 0x01}, /* CORE */ - { { PROC_TB_CORE0 }, 0x20, 0x01, 0x00}, - { { PROC_TB_CORE1 }, 0x20, 0x02, 0x00}, + { { PROC_TB_CORE0 }, 0x00, 0x20, 0x41}, + { { PROC_TB_CORE1 }, 0x00, 0x20, 0x42}, }; -#define ARRAY_SIZE(array) (sizeof(array) / sizeof(array[0])) - class TraceArrayFinder { public: @@ -186,24 +183,15 @@ class TraceArrayFinder { if(l_ta_def.bus_ids[sel] == i_trace_bus) { - fapi2::buffer<uint32_t> l_buffer; - l_buffer.insert<0, 8>(l_ta_def.chiplet); + uint32_t l_buffer = 0; + l_buffer |= l_ta_def.chiplet << 24; debug_scom_base = l_buffer | TA_DEBUG_BASE_SCOM; trace_scom_base = l_buffer | (TA_TRACE_BASE_SCOM + TA_BASE_SCOM_MULTIPLIER * l_ta_def.base_multiplier); - - // Special handling Core - if(l_ta_def.chiplet == 0x20) - { - trace_scom_base &= 0x00FFFFFF; - } - - ex_odd_scom_offset = TA_EX_OFFSET_MULTIPLIER * - l_ta_def.ex_multiplier; - + ex_odd_scom_offset = l_ta_def.ex_odd_scom_offset; mux_sel = sel; return; } @@ -217,7 +205,7 @@ class TraceArrayFinder //----------------------------------------------------------------------------- fapi2::ReturnCode p9_sbe_tracearray( const fapi2::Target<P9_SBE_TRACEARRAY_TARGET_TYPES>& i_target, - const p9_sbe_tracearray_args& i_args, + const proc_gettracearray_args& i_args, uint64_t* o_ta_data, const uint32_t i_cur_row, const uint32_t i_num_rows @@ -235,15 +223,28 @@ fapi2::ReturnCode p9_sbe_tracearray( const uint32_t DEBUG_TRACE_CONTROL = l_ta_finder.debug_scom_base + DEBUG_TRACE_CONTROL_OFS; const uint32_t TRACE_SCOM_BASE = l_ta_finder.trace_scom_base; - const uint32_t TRACE_SCOM_OFFSET = l_ta_finder.ex_odd_scom_offset; + uint32_t tra_scom_offset = 0; + uint32_t l_proc_offset = 0; if ((arg_type & ta_type) == 0) { - FAPI_ERR("Specified trace array requires target type 0x%X," + FAPI_ERR("Specified trace array requires target type 0x%X, " "but the supplied target is of type 0x%X", ta_type, arg_type); return fapi2::RC_PROC_GETTRACEARRAY_INVALID_TARGET; } + /* There is no support for OBUS and MCBIST on SBE. + * These are passed as PERV targets, but have to be converted to + * PROC with manual address offset for chiplet, as trace scoms + * are not allowed for PERV targets in Cronus */ + const uint8_t l_chiplet_num = i_target.getChipletNumber(); + + if(IS_MCBIST(l_chiplet_num) || IS_OBUS(l_chiplet_num)) + { + target = i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>(); + l_proc_offset = (l_chiplet_num << 24) - (TRACE_SCOM_BASE & 0xFF000000); + } + /* Nimbus DD1 core traces can't be read out via SCOM. * Check an EC feature to see if that's fixed. */ if (ta_type == fapi2::TARGET_TYPE_CORE) @@ -254,12 +255,12 @@ fapi2::ReturnCode p9_sbe_tracearray( i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>(); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_CORE_TRACE_SCOMABLE, proc_target, l_core_trace_scomable), - "Failed to query chip EC feature" + "Failed to query chip EC feature " "ATTR_CHIP_EC_FEATURE_CORE_TRACE_SCOMABLE"); if (!l_core_trace_scomable) { - FAPI_ERR("Core arrays cannot be dumped in this chip EC;" + FAPI_ERR("Core arrays cannot be dumped in this chip EC; " "please use fastarray instead."); return fapi2::RC_PROC_GETTRACEARRAY_CORE_NOT_DUMPABLE; } @@ -270,6 +271,23 @@ fapi2::ReturnCode p9_sbe_tracearray( if (ta_type == fapi2::TARGET_TYPE_EX) { target = i_target.getParent<fapi2::TARGET_TYPE_EQ>(); + uint8_t l_chipunit_num; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, + i_target, + l_chipunit_num), + "Failed to get chipUnit ID from EX target"); + + if (l_chipunit_num & 1) + { + if(l_ta_finder.ex_odd_scom_offset == 0x01) + { + tra_scom_offset = EX_L21_SCOM_OFFSET; + } + else if(l_ta_finder.ex_odd_scom_offset == 0x02) + { + tra_scom_offset = EX_L31_SCOM_OFFSET; + } + } } /* Check that the trace mux is set up as expected */ @@ -277,7 +295,10 @@ fapi2::ReturnCode p9_sbe_tracearray( { fapi2::buffer<uint64_t> buf; FAPI_TRY(fapi2::getScom(target, - TRACE_SCOM_BASE + TRACE_SCOM_OFFSET + TRACE_TRCTRL_CONFIG_OFS, + (TRACE_SCOM_BASE + + tra_scom_offset + + TRACE_TRCTRL_CONFIG_OFS + + l_proc_offset), buf), "Failed to read current trace mux setting"); uint32_t cur_sel = 0; @@ -295,25 +316,29 @@ fapi2::ReturnCode p9_sbe_tracearray( /* If control is requested along with dump, pre dump condition * should run only once. * */ - if (i_args.stop_pre_dump && (!i_args.collect_dump || (i_cur_row == 0))) + if (i_args.stop_pre_dump && (!i_args.collect_dump || + (i_cur_row == P9_TRACEARRAY_FIRST_ROW))) { FAPI_DBG("Stopping trace arrays"); fapi2::buffer<uint64_t> buf; buf.flush<0>().setBit<DEBUG_TRACE_CONTROL_STOP>(); - FAPI_TRY(fapi2::putScom(target, DEBUG_TRACE_CONTROL, buf), + FAPI_TRY(fapi2::putScom(target, DEBUG_TRACE_CONTROL + l_proc_offset, buf), "Failed to stop chiplet domain trace arrays"); } if (i_args.collect_dump) { - fapi2::buffer<uint64_t> buf; + fapi2::buffer<uint64_t> buf = 0; /* Start with the low data register because that's where the * "trace running" bit is. */ for (uint32_t i = 0; i < i_num_rows; i++) { FAPI_TRY(fapi2::getScom(target, - TRACE_SCOM_BASE + TRACE_SCOM_OFFSET + TRACE_LO_DATA_OFS, + (TRACE_SCOM_BASE + + tra_scom_offset + + TRACE_LO_DATA_OFS + + l_proc_offset), buf), "Failed to read trace array low data register," " iteration %d", i); @@ -324,13 +349,13 @@ fapi2::ReturnCode p9_sbe_tracearray( * so it's okay to bail out. */ if (buf.getBit<TRACE_LO_DATA_RUNNING>()) { - FAPI_ERR("Trace array is still running -- " + FAPI_ERR("Trace array is still running --" " If you think you stopped it, maybe the controlling " "debug macro is slaved to another debug macro?"); return fapi2::RC_PROC_GETTRACEARRAY_TRACE_RUNNING; } - *((uint64_t*)o_ta_data + (2 * i + 1)) = buf; + *(o_ta_data + (2 * i + 1)) = buf; } /* @@ -341,18 +366,27 @@ fapi2::ReturnCode p9_sbe_tracearray( for (uint32_t i = 0; i < (P9_TRACEARRAY_NUM_ROWS - i_num_rows); i++) { FAPI_TRY(fapi2::getScom(target, - TRACE_SCOM_BASE + TRACE_SCOM_OFFSET + TRACE_LO_DATA_OFS, + (TRACE_SCOM_BASE + + tra_scom_offset + + TRACE_LO_DATA_OFS + + l_proc_offset), buf), - "Failed to read trace array low data register, iteration %d", i); + "Failed to read trace array low data register, " + "iteration %d", i); } /* Then dump the high data */ for (uint32_t i = 0; i < i_num_rows; i++) { FAPI_TRY(fapi2::getScom(target, - TRACE_SCOM_BASE + TRACE_SCOM_OFFSET + TRACE_HI_DATA_OFS, buf), - "Failed to read trace array high data register, iteration %d", i); - *((uint64_t*)o_ta_data + (2 * i + 0)) = buf; + (TRACE_SCOM_BASE + + tra_scom_offset + + TRACE_HI_DATA_OFS + + l_proc_offset), + buf), + "Failed to read trace array high data register, " + "iteration %d", i); + *(o_ta_data + (2 * i + 0)) = buf; } } @@ -360,22 +394,24 @@ fapi2::ReturnCode p9_sbe_tracearray( * only after all the P9_TRACEARRAY_NUM_ROWS rows are read. * */ if (i_args.reset_post_dump && - (!i_args.collect_dump || (i_cur_row >= P9_TRACEARRAY_NUM_ROWS))) + (!i_args.collect_dump || + ((i_cur_row + i_num_rows) >= P9_TRACEARRAY_NUM_ROWS))) { FAPI_DBG("Resetting trace arrays"); fapi2::buffer<uint64_t> buf; buf.flush<0>().setBit<DEBUG_TRACE_CONTROL_RESET>(); - FAPI_TRY(fapi2::putScom(target, DEBUG_TRACE_CONTROL, buf), + FAPI_TRY(fapi2::putScom(target, DEBUG_TRACE_CONTROL + l_proc_offset, buf), "Failed to reset chiplet domain trace arrays"); } if (i_args.restart_post_dump && - (!i_args.collect_dump || (i_cur_row >= P9_TRACEARRAY_NUM_ROWS))) + (!i_args.collect_dump || + ((i_cur_row + i_num_rows) >= P9_TRACEARRAY_NUM_ROWS))) { FAPI_DBG("Starting trace arrays"); fapi2::buffer<uint64_t> buf; buf.flush<0>().setBit<DEBUG_TRACE_CONTROL_START>(); - FAPI_TRY(fapi2::putScom(target, DEBUG_TRACE_CONTROL, buf), + FAPI_TRY(fapi2::putScom(target, DEBUG_TRACE_CONTROL + l_proc_offset, buf), "Failed to restart chiplet domain trace arrays"); } diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tracearray.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tracearray.H index fbb1e4709..0143ef64a 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tracearray.H +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tracearray.H @@ -43,8 +43,8 @@ // *HWP HW Backup Owner : Joe McGill <jmcgill@us.ibm.com> // *HWP FW Owner : Shakeeb Pasha<shakeebbk@in.ibm.com> // *HWP Team : Perv -// *HWP Level : 1 -// *HWP Consumed by : SBE +// *HWP Level : 2 +// *HWP Consumed by : Conus, SBE //------------------------------------------------------------------------------ #ifndef _P9_SBE_TRACEARRAY_H @@ -56,8 +56,22 @@ #include <fapi2.H> #include "p9_tracearray_defs.H" +constexpr uint32_t P9_TRACEARRAY_FIRST_ROW = 0; +constexpr uint32_t MCBIST_CHIPLET_ID_START = 0x07; +constexpr uint32_t MCBIST_CHIPLET_ID_END = 0x08; +constexpr uint32_t OBUS_CHIPLET_ID_START = 0x09; +constexpr uint32_t OBUS_CHIPLET_ID_END = 0x0C; + +#define IS_MCBIST(chipletId) \ + ((chipletId >= MCBIST_CHIPLET_ID_START) && \ + (chipletId <= MCBIST_CHIPLET_ID_END)) + +#define IS_OBUS(chipletId) \ + ((chipletId >= OBUS_CHIPLET_ID_START) && \ + (chipletId <= OBUS_CHIPLET_ID_END)) + // structure to represent HWP arguments -struct p9_sbe_tracearray_args +struct proc_gettracearray_args { p9_tracearray_bus_id trace_bus; ///< The trace bus whose associated trace array should be dumped bool stop_pre_dump; ///< Stop the trace array before starting the dump @@ -69,14 +83,16 @@ struct p9_sbe_tracearray_args static const fapi2::TargetType P9_SBE_TRACEARRAY_TARGET_TYPES = fapi2::TARGET_TYPE_PROC_CHIP | + fapi2::TARGET_TYPE_PERV | fapi2::TARGET_TYPE_EX | fapi2::TARGET_TYPE_CORE; //function pointer typedef definition for HWP call support typedef fapi2::ReturnCode (*p9_sbe_tracearray_FP_t) ( const fapi2::Target<P9_SBE_TRACEARRAY_TARGET_TYPES>& i_target, - const p9_sbe_tracearray_args& i_args, - uint8_t* o_ta_data, + const proc_gettracearray_args& i_args, + uint64_t* o_ta_data, + const uint32_t i_cur_row, const uint32_t i_num_rows ); @@ -89,16 +105,17 @@ extern "C" { * @return The type of target to hand to p9_sbe_tracearray to clearly * identify the array instance. */ - static inline fapi2::TargetType p9_sbe_tracearray_target_type(p9_tracearray_bus_id i_trace_bus) + static inline fapi2::TargetType p9_sbe_tracearray_target_type( + p9_tracearray_bus_id i_trace_bus) { - /* On SBE there is no support for MCBIST and OBUS fapi targets. - * But since the usage related to these targets in p9_sbe_tracearray - * is only for SCOMs with fully qualified adresses, PROC - * target is used for MCBIST and OBUS as well */ - if (i_trace_bus <= _PROC_TB_LAST_MC_TARGET) + if (i_trace_bus <= _PROC_TB_LAST_PROC_TARGET) { return fapi2::TARGET_TYPE_PROC_CHIP; } + else if (i_trace_bus <= _PROC_TB_LAST_MC_TARGET) + { + return fapi2::TARGET_TYPE_PERV; + } else if (i_trace_bus <= _PROC_TB_LAST_EX_TARGET) { return fapi2::TARGET_TYPE_EX; @@ -109,8 +126,6 @@ extern "C" { } } - - /* TODO via RTC:164528 - Look at optimization to improve performance * @brief Retrieve trace array data, based on the number of * rows requested, from selected trace array via SCOM. @@ -137,18 +152,22 @@ extern "C" { * if trace array dump sequence completes successfully, * RC_PROC_GETTRACEARRAY_INVALID_BUS * if an invalid trace bus ID has been requested + * RC_PROC_GETTRACEARRAY_INVALID_TARGET + * if the supplied target type does not match the requested trace bus * RC_PROC_GETTRACEARRAY_CORE_NOT_DUMPABLE * if a core trace array has been requested but the chip's core * is not dumpable via SCOM -> use fastarray instead + * RC_PROC_GETTRACEARRAY_TRACE_RUNNING + * if trace array is running when dump collection is attempted, * RC_PROC_GETTRACEARRAY_TRACE_MUX_INCORRECT * if the primary trace mux is not set up to trace the requested bus, * else FAPI getscom/putscom return code for failing operation */ fapi2::ReturnCode p9_sbe_tracearray( const fapi2::Target<P9_SBE_TRACEARRAY_TARGET_TYPES>& i_target, - const p9_sbe_tracearray_args& i_args, + const proc_gettracearray_args& i_args, uint64_t* o_ta_data, - const uint32_t i_cur_row = 0, + const uint32_t i_cur_row = P9_TRACEARRAY_FIRST_ROW, const uint32_t i_num_rows = P9_TRACEARRAY_NUM_ROWS ); } // extern "C" |