PM Recv FFDC: Base changes for PPE State and OCC Plat

Change to
1. enable collection of PPE XIRS, SPRs, GPRs to respective
2. create and collect OCC plat traces for OCC, GPE0/1 & Shared

to respective regions in HOMER PM FFDC sections

Change-Id: I4ee1314450b72818e4b3ba44558e1359a1a2df08
RTC: 180382
RTC: 180553
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47120
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47127
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

13 files changed, 626 insertions, 50 deletions

diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
index a7b34baab..791f7f2c8 100644
--- a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
@@ -543,14 +543,13 @@ HCD_CONST(PGPE_IMAGE_RESERVE_SIZE,
 HCD_CONST(FFDC_CME_MAGIC_NUM,         (0x434d455f)) //"CME_"
 HCD_CONST(FFDC_SGPE_MAGIC_NUM,        (0x53475045)) //"SGPE"
 HCD_CONST(FFDC_PGPE_MAGIC_NUM,        (0x50475045)) //"PGPE"
+HCD_CONST(FFDC_OCC_MAGIC_NUM,         (0x4f43435f)) //"OCC_"
 
 //FFDC Region Layout
 HCD_CONST(FFDC_PPE_SCORE_BOARD_SIZE,    0x200)
 HCD_CONST(FFDC_PPE_IMG_HDR_SIZE,        0x80)
 HCD_CONST(FFDC_PPE_XIR_SIZE,            0x28)
 HCD_CONST(FFDC_PPE_SPR_SIZE,            0x80)
-HCD_CONST(FFDC_PPE_MAJOR_SPR_SIZE,      0x38)
-HCD_CONST(FFDC_PPE_MINOR_SPR_SIZE,      0x38)
 HCD_CONST(FFDC_PPE_GPR_SIZE,            0x80)
 HCD_CONST(FFDC_PPE_INTERNAL_REG_SIZE,   0x78)
 HCD_CONST(FFDC_PPE_TRACES_SIZE,         0x200)
@@ -563,8 +562,7 @@ HCD_CONST(FFDC_HOMER_TOP_HEADER ,       0x38)
 HCD_CONST(FFDC_QUAD_REGION_SIZE,        0x10E8)
 HCD_CONST(FFDC_SGPE_REGION_SIZE,        (FFDC_PPE_BLOCK_SIZE))
 HCD_CONST(FFDC_PGPE_REGION_SIZE,        (FFDC_PPE_BLOCK_SIZE))
-HCD_CONST(FFDC_OCC_REGION_SIZE,         0x8610)
-HCD_CONST(FFDC_OCC_REGION_HDR_SIZE,     0x10)
+HCD_CONST(FFDC_OCC_REGION_HDR_SIZE,     0x18)
 HCD_CONST(FFDC_TRACE_ERR_SIZE,          (8 * ONE_KB))
 HCD_CONST(FFDC_TRACE_IMP_SIZE,          (FFDC_TRACE_ERR_SIZE))
 HCD_CONST(FFDC_TRACE_INF_SIZE,          (FFDC_TRACE_ERR_SIZE))
@@ -572,6 +570,16 @@ HCD_CONST(FFDC_TRACE_SSX_SIZE ,         (FFDC_TRACE_ERR_SIZE))
 HCD_CONST(FFDC_TRACE_GPE0_SIZE,         0x200)
 HCD_CONST(FFDC_TRACE_GPE1_SIZE,         0x200)
 HCD_CONST(FFDC_SHARED_SRAM_SIZE,        0x200)
+HCD_CONST(FFDC_OCC_REGS_SIZE,           0x580)
+HCD_CONST(FFDC_OCC_REGION_SIZE,         (FFDC_OCC_REGION_HDR_SIZE +
+          FFDC_TRACE_ERR_SIZE +
+          FFDC_TRACE_IMP_SIZE +
+          FFDC_TRACE_INF_SIZE +
+          FFDC_TRACE_SSX_SIZE +
+          FFDC_TRACE_GPE0_SIZE +
+          FFDC_TRACE_GPE1_SIZE +
+          FFDC_SHARED_SRAM_SIZE +
+          FFDC_OCC_REGS_SIZE))
 HCD_CONST(FFDC_REGION_QPMR_BASE_OFFSET, 0xE0000)
 HCD_CONST(FFDC_REGION_HOMER_BASE_OFFSET,
           (QPMR_HOMER_OFFSET + FFDC_REGION_QPMR_BASE_OFFSET))
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H
index 4bd6298c3..0b9119fc9 100644
--- a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H
@@ -48,6 +48,27 @@
 /// OCC SRAM
 
 HCD_CONST(OCC_SRAM_BASE_ADDR,                   0xFFF00000)
+HCD_CONST(GPE0_SRAM_BASE_ADDR,                  0xFFF01000)
+HCD_CONST(GPE1_SRAM_BASE_ADDR,                  0xFFF10000)
+
+/// Base Addresses for various traces regions in OCC SRAM
+HCD_CONST(OCC_SRAM_TRACE_BUF_BASE_SSX_PTR,      0xFFF40824)
+HCD_CONST(OCC_SRAM_TRACE_BUF_BASE_ERR,          0xFFFB4000)
+HCD_CONST(OCC_SRAM_TRACE_BUF_BASE_INF,          0xFFFB6000)
+HCD_CONST(OCC_SRAM_TRACE_BUF_BASE_IMP,          0xFFFB8000)
+// @TODO: HCD_CONST(OCC_SRAM_TRACE_BUF_BASE_SHARED,    0x0)
+HCD_CONST(GPE0_SRAM_TRACE_BUF_PTR,              GPE0_SRAM_BASE_ADDR + 0x184)
+HCD_CONST(GPE1_SRAM_TRACE_BUF_PTR,              GPE1_SRAM_BASE_ADDR + 0x184)
+
+// Size of various traces regions in OCC SRAM
+HCD_CONST(OCC_SRAM_TRACE_BUF_SSX_SIZE_PTR,      0xFFF40828)
+HCD_CONST(OCC_SRAM_TRACE_BUF_ERR_SIZE,          (8 * ONE_KB))
+HCD_CONST(OCC_SRAM_TRACE_BUF_INF_SIZE,          (8 * ONE_KB))
+HCD_CONST(OCC_SRAM_TRACE_BUF_IMP_SIZE,          (8 * ONE_KB))
+// @TODO: HCD_CONST(OCC_SRAM_TRACE_BUF_SHARED_SIZE, )
+HCD_CONST(GPE0_SRAM_TRACE_BUF_SIZE_PTR,         (GPE0_SRAM_BASE_ADDR + 0x188))
+HCD_CONST(GPE1_SRAM_TRACE_BUF_SIZE_PTR,         (GPE1_SRAM_BASE_ADDR + 0x188))
+
 HCD_CONST(OCC_SRAM_IPC_REGION_SIZE,             (4 * ONE_KB))
 HCD_CONST(OCC_SRAM_GPE0_REGION_SIZE,            (60 * ONE_KB))
 HCD_CONST(OCC_SRAM_GPE1_REGION_SIZE,            (64 * ONE_KB))
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_base.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_base.C
index 66089384b..7ecb814f4 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_base.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_base.C
@@ -26,6 +26,7 @@
 
 #include <p9_pm_recovery_ffdc_base.H>
 #include <p9_pm_recovery_ffdc_defines.H>
+#include <p9_ppe_state.H>
 #include <endian.h>
 #include <stddef.h>
 
@@ -45,7 +46,7 @@
 
     fapi2::ReturnCode PlatPmComplex::collectFfdc( void * i_pHomerBuf )
     {
-        FAPI_DBG("<< PlatPmComplex::collectFfdc");
+        FAPI_DBG(">> PlatPmComplex::collectFfdc");
 
         FAPI_DBG("<< PlatPmComplex::collectFfdc");
         return fapi2::FAPI2_RC_SUCCESS;;
@@ -107,8 +108,107 @@
         return fapi2::FAPI2_RC_SUCCESS;
     }
 
-    //---------------------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+    // @TODO May need to port this away, based on discussion
+    fapi2::ReturnCode PlatPmComplex::readPpeHaltState (
+                      const uint64_t i_xirBaseAddress,
+                      uint8_t&       o_ppeHaltState )
+    {
+        FAPI_DBG ( ">> PlatPmComplex::getPpeHaltState XIR Base: 0x%08llX",
+                   i_xirBaseAddress );
+
+        fapi2::ReturnCode l_rc;
+        fapi2::buffer<uint64_t> l_data64;
+
+        o_ppeHaltState = PPE_HALT_COND_UNKNOWN;
+
+        // Read the PPE XIR pair for XSR+SPRG0
+        l_rc = getScom ( iv_procChip,
+                         (i_xirBaseAddress + PPE_XIRAMDBG),
+                         l_data64 );
+
+        if ( l_rc == fapi2::FAPI2_RC_SUCCESS )
+        {   // PU_PPE_XIRAMDBG_XSR_HS
+            if ( l_data64.getBit (0, 1) )
+            {   // Halt exists, get all bits 0:3
+                l_data64.getBit (PU_PPE_XIRAMDBG_XSR_HS, 4);
+                o_ppeHaltState = static_cast<uint8_t> (l_data64());
+            }
+            else
+            {   // PPE is not halted
+                o_ppeHaltState = PPE_HALT_COND_NONE;
+            }
+        }
+        else
+        {
+            FAPI_ERR ("::readPpeHaltState: Error reading PPE XIRAMDBG");
+        }
+
+        FAPI_DBG ( "<< PlatPmComplex::getPpeHaltState: 0x%02X",
+                   o_ppeHaltState );
+        return fapi2::FAPI2_RC_SUCCESS;
+    }
+
+//------------------------------------------------------------------------------
+    // @TODO Ideally, the reset flow should have already halted the PPE.
+    // Should the default mode here be FORCE_HALT? Is that safe?
+    fapi2::ReturnCode PlatPmComplex::collectPpeState (
+                      const uint64_t i_xirBaseAddress,
+                      const uint8_t* i_pHomerOffset,
+                      const PPE_DUMP_MODE i_mode )
+    {
+        FAPI_DBG (">> PlatPmComplex:collectPpeState");
+        PpeFfdcLayout* l_pPpeFfdc = (PpeFfdcLayout*) (i_pHomerOffset);
+        PPERegValue_t* l_pPpeRegVal = NULL;
+
+        std::vector<PPERegValue_t> l_vSprs;
+        std::vector<PPERegValue_t> l_vGprs;
+        std::vector<PPERegValue_t> l_vXirs;
+
+        // @TODO Update the ppe_halt HWP to avoid halting the PPE again
+        // if it is already halted. Can potentially change the XSR?
+        FAPI_TRY ( p9_ppe_state (
+                   iv_procChip,
+                   i_xirBaseAddress,
+                   i_mode,
+                   l_vSprs,
+                   l_vXirs,
+                   l_vGprs) );
+
+        // @TODO any faster way, e.g. use data() method and memcpy?
+        l_pPpeRegVal = (PPERegValue_t*) &l_pPpeFfdc->iv_ppeXirReg[0];
+        for ( auto& it : l_vXirs )
+        {
+            l_pPpeRegVal->number = it.number;
+            l_pPpeRegVal->value = it.value;
+            ++l_pPpeRegVal;
+        }
 
+        l_pPpeRegVal = (PPERegValue_t*) &l_pPpeFfdc->iv_ppeSpr[0];
+        for ( auto& it : l_vSprs )
+        {
+            l_pPpeRegVal->number = it.number;
+            l_pPpeRegVal->value = it.value;
+            ++l_pPpeRegVal;
+        }
+
+        l_pPpeRegVal = (PPERegValue_t*) &l_pPpeFfdc->iv_ppeGprs[0];
+        for ( auto& it : l_vGprs )
+        {
+            l_pPpeRegVal->number = it.number;
+            l_pPpeRegVal->value = it.value;
+            ++l_pPpeRegVal;
+        }
+
+    fapi_try_exit:
+        FAPI_DBG ( "<< PlatPmComplex::collectPpeState XIRs:%d SPRs:%d GPRs:%d",
+                   l_vXirs.size(), l_vSprs.size(), l_vGprs.size() );
+
+       return fapi2::current_err;
+    }
+
+
+    //---------------------------------------------------------------------------------------------
     fapi2::ReturnCode PlatPmComplex::collectSramInfo( const fapi2::Target< fapi2::TARGET_TYPE_EX > & i_exTgt,
                                                       uint8_t * i_pSramData,
                                                       FfdcDataType i_dataType,
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_base.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_base.H
index 1bd740785..711ebeb80 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_base.H
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_base.H
@@ -48,6 +48,7 @@
 #include <p9_pm_ocb_indir_access.H>
 #include <p9_cme_sram_access.H>
 #include <p9_pm_ocb_indir_setup_linear.H>
+#include <p9_ppe_utils.H>
 
 namespace p9_stop_recov_ffdc
 {
@@ -73,19 +74,40 @@ namespace p9_stop_recov_ffdc
             //  @return     fapi2 return code.
             virtual fapi2::ReturnCode collectFfdc( void* i_pHomerBuf );
 
+            /// @brief  sets start address of platform's trace buffer.
+            void setTraceBufAddr (uint32_t i_addr)
+            { iv_traceBufBaseAddress = i_addr; }
+
             ///@brief returns instance id.
             PmComplexPlatId getPlatId() { return iv_plat ; }
 
             /// @brief returns proc chip target associated with platform
             fapi2::Target< fapi2::TARGET_TYPE_PROC_CHIP > getProcChip() const { return iv_procChip; }
 
-            protected:
+        protected:
+            ///@brief reads the PPE Halt State from XSR, w/o halting the PPE
+            ///@param[in]  i_xirBaseAddress XCR SCOM Address of the PPE
+            ///@param[out] o_haltCondition  p9_stop_recov_ffdc::PpeHaltCondition
+            ///@return  fapi2 return code
+            fapi2::ReturnCode readPpeHaltState (
+                      const uint64_t i_xirBaseAddress,
+                      uint8_t&       o_haltCondition );
+
+            ///@brief collects PPE State (XIRs, SPRs, GPRs) to a loc in HOMER
+            ///@param[in] i_xirBaseAddress XCR SCOM Address of the PPE
+            ///@param[in] i_pHomerOffset   PPE section base address in HOMER
+            ///@param[in] i_mode           PPE_DUMP_MODE, defaults to HALT
+            ///@return  fapi2 return code
+            fapi2::ReturnCode collectPpeState (
+                   const uint64_t i_xirBaseAddress,
+                   const uint8_t* i_pHomerOffset,
+                   const PPE_DUMP_MODE i_mode = HALT );
 
             ///@brief collects FFDC from CME/OCC SRAM
             ///@param[in]   i_chipletTarget     fapi2 target for EX or Proc
             ///@param[in]   i_pSramData         points to HOMER location containing SRAM contents
             ///@param[in]   i_dataType          type of FFDC data
-            ///@param[in]   i_sramLength        length of SRAM FFDC
+            ///@param[in]   i_sramLength        length of SRAM FFDC in bytes
             ///@return  fapi2 return code
             fapi2::ReturnCode collectSramInfo( const fapi2::Target< fapi2::TARGET_TYPE_EX >& i_exTgt,
                                                uint8_t * i_pSramData,
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_base.mk b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_base.mk
index 4aae5979c..5adde6809 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_base.mk
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_base.mk
@@ -26,5 +26,6 @@ PROCEDURE = p9_pm_recovery_ffdc_base
 FFDC_INC=$(ROOTPATH)/chips/p9/procedures/hwp/lib/
 lib$(PROCEDURE)_DEPLIBS+=p9_pm_ocb_indir_setup_linear
 lib$(PROCEDURE)_DEPLIBS+=p9_cme_sram_access
+lib$(PROCEDURE)_DEPLIBS+=p9_ppe_state
 $(call ADD_MODULE_INCDIR,$(FFDC_INC))
 $(call BUILD_PROCEDURE)
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_cme.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_cme.C
index b22fc92f4..0f49b63dc 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_cme.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_cme.C
@@ -42,6 +42,7 @@
 
 #include <p9_pm_recovery_ffdc_cme.H>
 #include <p9_hcd_memmap_cme_sram.H>
+#include <p9_ppe_defs.H>
 #include <stddef.h>
 #include <endian.h>
 
@@ -67,7 +68,7 @@
         uint8_t l_exPos   = 0;
         uint8_t l_cmePos  = 0;
         uint8_t l_ffdcValdityVect = PPE_FFDC_ALL_VALID;
-        uint8_t l_haltState = 0; //FIXME Needs update when PPE State gets handled
+        uint8_t l_haltState = PPE_HALT_COND_UNKNOWN;
         uint8_t *l_pFfdcLoc = NULL;
         HomerFfdcRegion * l_pHomerFfdc =
                 ( HomerFfdcRegion *)( (uint8_t *)i_pHomerBuf + FFDC_REGION_HOMER_BASE_OFFSET );
@@ -95,6 +96,22 @@
 
             //In case of error , invalidate FFDC in header.
 
+            // @TODO this is still after reset, which would have already
+            // halted the ppe. We need a wa to record this before reset
+            // and pass it down, or have a spl r-m-w update per member
+            // of the PPE Header?
+            // l_retCode = getPpeHaltState (
+            //             getCmeBaseAddress (l_cmePos),
+            //             l_haltState);
+
+            l_retCode = collectPpeState ( getCmeBaseAddress (l_cmePos),
+                                          l_pFfdcLoc );
+            if ( l_retCode != fapi2::FAPI2_RC_SUCCESS )
+            {
+                FAPI_ERR ( "Error collecting CME State, CME Pos 0x08x",
+                           l_cmePos );
+                l_ffdcValdityVect &= ~PPE_STATE_VALID;
+            }
             l_retCode = collectTrace( l_pFfdcLoc, ex );
 
             if( l_retCode )
@@ -173,14 +190,6 @@
 
     //-----------------------------------------------------------------------
 
-    fapi2::ReturnCode  PlatCme::collectCmeState( uint8_t * i_pCmeState,
-                                                 const fapi2::Target<fapi2::TARGET_TYPE_EX >& i_exTgt )
-    {
-        return fapi2::FAPI2_RC_SUCCESS;
-    }
-
-    //-----------------------------------------------------------------------
-
     fapi2::ReturnCode PlatCme::collectInternalReg( uint8_t * i_pCmeIntReg,
                                                    const fapi2::Target<fapi2::TARGET_TYPE_EX >& i_exTgt )
     {
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_cme.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_cme.H
index be93db6bf..a9ad0f0c4 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_cme.H
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_cme.H
@@ -73,12 +73,6 @@ namespace p9_stop_recov_ffdc
             fapi2::ReturnCode  collectGlobals( uint8_t * i_pHomerBuf,
                                                const fapi2::Target< fapi2::TARGET_TYPE_EX > & i_exTgt );
 
-            /// @brief      collects CME state for a given CME.
-            /// @param[in]  i_pHomerBuf     points to location of HOMER meant for CME's state.
-            /// @param[in]  i_exTgt         fapi2 target for ex
-            fapi2::ReturnCode  collectCmeState( uint8_t * i_pHomerBuf ,
-                                                const fapi2::Target< fapi2::TARGET_TYPE_EX > & i_exTgt);
-
             /// @brief      collects internal register info for a given CME
             /// @param[in]  i_pHomerBuf     points to location of HOMER meant for CME's internal register.
             /// @param[in]  i_exTgt         fapi2 target for ex
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_defines.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_defines.H
index 6c72fb709..cde15a590 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_defines.H
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_defines.H
@@ -72,13 +72,30 @@ enum PpeFfdcValidStatus
     PPE_DASHBOARD_VALID     =   0x01,  // PPE globals are valid
     PPE_IMAGE_HEADER_VALID  =   0x02,  // PPE image header is valid
     PPE_TRACE_VALID         =   0x04,  // PPE Traces are valid
-    PPE_SPR_VALID           =   0x08,  // PPE SPRs are valid
+    PPE_STATE_VALID         =   0x08,  // PPE XIRS, GPES and SPRs are valid
     PPE_INT_REG_VALID       =   0x10,  // PPE Int Regs are valid
-    PPE_STATE_VALID         =   0x20,  // PPE State Info is valid
+    PPE_HALT_STATE_VALID    =   0x20,  // PPE Halt State Info is valid
     PPE_FFDC_ALL_VALID      =   0x3F,  // Entire PPE FFDC is valid
 };
 
 /**
+ * @brief enumerates PPE's HALT conditions as inteprreted from XSR[0:3]
+ */
+enum PpeHaltCondition
+{
+    PPE_HALT_COND_NONE    = 0x00, // Not halted
+    PPE_HALT_COND_BAD     = 0x08, // Halted, but cannot map source
+    PPE_HALT_COND_XCR     = 0x09, // Halted via XCR
+    PPE_HALT_COND_WDT     = 0x0A, // Halted via Watch Dog
+    PPE_HALT_COND_NMI     = 0x0B, // Halted via unmaskable intr
+    PPE_HALT_COND_DBG     = 0x0C, // Debug halt
+    PPE_HALT_COND_DBCR    = 0x0D, // Halt via Debug Control Reg
+    PPE_HALT_COND_EXT_HLT = 0x0E, // Ext halt_req input active
+    PPE_HALT_COND_HW      = 0x0F, // Halted with a HW failure
+    PPE_HALT_COND_UNKNOWN = 0xFF  // Could not read or interpret XSR
+};
+
+/**
  * @brief   models header of FFDC region of HOMER associated with a CME.
  */
 struct __attribute__((packed)) PpeFfdcHeader
@@ -116,8 +133,53 @@ struct __attribute__((packed)) QuadFfdcHeader
     uint8_t  iv_reserve[2];
 };
 
+
 /**
- * @brief   a union modelling CME FFDC region's header area.
+ * @brief enumerates bit position used as validity mark of OCC FFDC sub-section.
+ */
+enum OccFfdcValidStatus
+{
+    OCC_FFDC_INVALID             =   0x00,  // None of the FFDC section is valid
+    OCC_FFDC_TRACE_ERR_VALID     =   0x01,  // OCC ERR traces section valid
+    OCC_FFDC_TRACE_IMP_VALID     =   0x02,  // OCC IMP traces section valid
+    OCC_FFDC_TRACE_INF_VALID     =   0x04,  // OCC INF traces section valid
+    OCC_FFDC_TRACE_SSX_VALID     =   0x08,  // OCC SSX trace section valid
+    OCC_FFDC_TRACE_GPE0_VALID    =   0x10,  // OCC GPE0 Trace Section valid
+    OCC_FFDC_TRACE_GPE1_VALID    =   0x20,  // OCC GPE1 Trace Section Valid
+    OCC_FFDC_SHARED_REGION_VALID =   0x40,  // OCC Shared Region Section valid
+    OCC_FFDC_REGISTERS_VALID     =   0x80,  // OCC Register Section valid
+    OCC_FFDC_VALID_ALL           =   ( OCC_FFDC_TRACE_ERR_VALID |
+                                       OCC_FFDC_TRACE_IMP_VALID |
+                                       OCC_FFDC_TRACE_INF_VALID |
+                                       OCC_FFDC_TRACE_SSX_VALID |
+                                       OCC_FFDC_TRACE_GPE0_VALID |
+                                       OCC_FFDC_TRACE_GPE1_VALID |
+                                       OCC_FFDC_SHARED_REGION_VALID |
+                                       OCC_FFDC_REGISTERS_VALID )
+};
+
+
+/**
+ *  * @brief models OCC Region FFDC header.
+ *   */
+struct __attribute__((packed)) OccFfdcHeader
+{
+    uint32_t iv_magicWord;
+    uint8_t  iv_ffdcValid;
+    uint8_t  iv_headerSize;
+    uint16_t iv_sectionSize;
+    uint16_t iv_offsetErrTrace;
+    uint16_t iv_offsetImpTrace;
+    uint16_t iv_offsetInfTrace;
+    uint16_t iv_offsetSsxTrace;
+    uint16_t iv_offsetGpe0Trace;
+    uint16_t iv_offsetGpe1Trace;
+    uint16_t iv_offsetSharedSram;
+    uint16_t iv_offsetOccRegs;
+};
+
+/**
+ * @brief   a union modelling PPE FFDC region's header area.
  */
 union PpeFfdcHdrRegion
 {
@@ -126,6 +188,15 @@ union PpeFfdcHdrRegion
 };
 
 /**
+ *  * @brief   a union modelling OCC FFDC region's header area.
+ *   */
+union OccFfdcHdrRegion
+{
+    uint8_t iv_ppeFfdcHdrArea[FFDC_OCC_REGION_HDR_SIZE];
+    OccFfdcHeader iv_occFfdcHdr;
+};
+
+/**
  * @brief   models CME's FFDC region.
  */
 struct  __attribute__((packed)) PpeFfdcLayout
@@ -134,8 +205,7 @@ struct  __attribute__((packed)) PpeFfdcLayout
     uint8_t iv_ppeGlobals[FFDC_PPE_SCORE_BOARD_SIZE];
     uint8_t iv_ppeImageHeader[FFDC_PPE_IMG_HDR_SIZE];
     uint8_t iv_ppeXirReg[FFDC_PPE_XIR_SIZE];
-    uint8_t iv_ppeMajSpr[FFDC_PPE_MAJOR_SPR_SIZE];
-    uint8_t iv_ppeMinSpr[FFDC_PPE_MINOR_SPR_SIZE];
+    uint8_t iv_ppeSpr[FFDC_PPE_SPR_SIZE];
     uint8_t iv_ppeGprs[FFDC_PPE_GPR_SIZE];
     uint8_t iv_ppeInternalReg[FFDC_PPE_INTERNAL_REG_SIZE];
     uint8_t iv_ppeTraces[FFDC_PPE_TRACES_SIZE];
@@ -155,16 +225,17 @@ struct __attribute__((packed)) HomerQuadFfdcRegion
 /**
  * @brief   models OCC FFDC region of HOMER.
  */
-struct __attribute__((packed)) HomerOccFfdcRegion
+struct __attribute__((packed)) OccFfdcRegion
 {
     uint8_t iv_occFfdcHeader[FFDC_OCC_REGION_HDR_SIZE];
-    uint8_t iv_occTraceErrSize[FFDC_TRACE_ERR_SIZE];
-    uint8_t iv_occTraceImpSize[FFDC_TRACE_IMP_SIZE];
-    uint8_t iv_occTraceInfSize[FFDC_TRACE_INF_SIZE];
-    uint8_t iv_occSsxSize[FFDC_TRACE_SSX_SIZE];
-    uint8_t iv_occTraceGpe0Size[FFDC_TRACE_GPE0_SIZE];
-    uint8_t iv_occTraceGpe1Size[FFDC_TRACE_GPE1_SIZE];
-    uint8_t iv_occSharedSramSize[FFDC_SHARED_SRAM_SIZE];
+    uint8_t iv_occTraceErr[FFDC_TRACE_ERR_SIZE];
+    uint8_t iv_occTraceImp[FFDC_TRACE_IMP_SIZE];
+    uint8_t iv_occTraceInf[FFDC_TRACE_INF_SIZE];
+    uint8_t iv_occTraceSsx[FFDC_TRACE_SSX_SIZE];
+    uint8_t iv_occTraceGpe0[FFDC_TRACE_GPE0_SIZE];
+    uint8_t iv_occTraceGpe1[FFDC_TRACE_GPE1_SIZE];
+    uint8_t iv_occSharedSram[FFDC_SHARED_SRAM_SIZE];
+    uint8_t iv_occRegs[FFDC_OCC_REGS_SIZE];
 };
 
 /**
@@ -176,7 +247,7 @@ struct  __attribute__((packed)) HomerFfdcRegion
     HomerQuadFfdcRegion iv_quadFfdc[MAX_QUADS_PER_CHIP];
     PpeFfdcLayout       iv_sgpeFfdcRegion;
     PpeFfdcLayout       iv_pgpeFfdcRegion;
-    HomerOccFfdcRegion  iv_occFfdcRegion;
+    OccFfdcRegion       iv_occFfdcRegion;
 };
 
 }   //namespace p9_stop_recov_ffdc ends
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_occ.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_occ.C
new file mode 100644
index 000000000..2921efe67
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_occ.C
@@ -0,0 +1,230 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_occ.C $ */
+/*                                                                        */
+/* OpenPOWER HostBoot Project                                             */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// *INDENT-OFF*
+
+
+///
+/// @file   p9_pm_recovery_ffdc_occ.C
+/// @brief  Model OCC platform for the FFDC collection of PM complex
+///
+/// *HWP HWP Owner:      Greg Still <stillgs@us.ibm.com>
+/// *HWP FW Owner:       Amit Tendolkar <amit.tendolkar@in.ibm.com>
+/// *HWP Team:           PM
+/// *HWP Level:          2
+/// *HWP Consumed by:    Hostboot
+//
+// *INDENT-OFF*
+//--------------------------------------------------------------------------
+// Includes
+//--------------------------------------------------------------------------
+
+#include <p9_pm_recovery_ffdc_occ.H>
+#include <p9_hcd_memmap_occ_sram.H>
+#include <p9_ppe_defs.H>
+#include <stddef.h>
+#include <endian.h>
+
+ namespace p9_stop_recov_ffdc
+ {
+    PlatOcc::PlatOcc (
+    const fapi2::Target< fapi2::TARGET_TYPE_PROC_CHIP > i_procChipTgt ) :
+    PlatPmComplex(i_procChipTgt, 0, 0, 0, PLAT_OCC)
+    { }
+
+    //----------------------------------------------------------------------
+
+    fapi2::ReturnCode PlatOcc::collectFfdc( void * i_pHomerBuf )
+    {
+        FAPI_DBG(">> PlatOcc::collectFfdc");
+        fapi2::ReturnCode l_retCode = fapi2::FAPI2_RC_SUCCESS;
+        uint8_t l_ffdcValid = OCC_FFDC_INVALID;
+        uint8_t* l_pFfdcLoc = NULL;
+
+        HomerFfdcRegion* l_pHomerFfdc = (HomerFfdcRegion*)
+             ((uint8_t*) i_pHomerBuf + FFDC_REGION_HOMER_BASE_OFFSET );
+
+        l_pFfdcLoc = (uint8_t*) (&l_pHomerFfdc->iv_occFfdcRegion);
+
+        l_retCode = collectTrace (l_pFfdcLoc, OCC_SRAM_TRACE_BUF_BASE_ERR);
+        if( l_retCode )
+        {
+            FAPI_ERR ("Error collecting OCC ERR Traces");
+        }
+        l_ffdcValid |= OCC_FFDC_TRACE_ERR_VALID;
+
+        l_retCode = collectTrace (l_pFfdcLoc, OCC_SRAM_TRACE_BUF_BASE_IMP);
+        if( l_retCode )
+        {
+            FAPI_ERR ("Error collecting OCC IMP Traces");
+        }
+        l_ffdcValid |= OCC_FFDC_TRACE_IMP_VALID;
+
+        l_retCode = collectTrace (l_pFfdcLoc, OCC_SRAM_TRACE_BUF_BASE_INF);
+        if( l_retCode )
+        {
+            FAPI_ERR ("Error collecting OCC INF Traces");
+        }
+        l_ffdcValid |= OCC_FFDC_TRACE_INF_VALID;
+
+        // @TODO Read SRAM for Base and Size of other undefined regions
+        //       before collectTrace
+
+        // @TODO Collect OCC Registers
+
+        FAPI_TRY( updateOccFfdcHeader( l_pFfdcLoc, l_ffdcValid ),
+                          "Failed To Update OCC FFDC Header for OCC" );
+
+    fapi_try_exit:
+        FAPI_DBG("<< PlatSgpe::collectFfdc");
+        return fapi2::current_err;
+    }
+
+    //-----------------------------------------------------------------------
+
+    fapi2::ReturnCode PlatOcc::collectTrace ( uint8_t* i_pTraceBuf,
+                                              uint32_t i_sramAddr )
+    {
+        FAPI_DBG ( ">> PlatOcc::collectTrace: 0x%08X",
+                   i_sramAddr );
+
+        OccFfdcRegion* l_pOccFfdc = ( OccFfdcRegion*) (i_pTraceBuf);
+        uint8_t* l_pTraceLoc = NULL;
+        uint32_t l_len = 0;
+
+        switch (i_sramAddr)
+        {
+            case OCC_SRAM_TRACE_BUF_BASE_ERR:
+                l_pTraceLoc = &l_pOccFfdc->iv_occTraceErr[0];
+                setTraceBufAddr (OCC_SRAM_TRACE_BUF_BASE_ERR);
+                l_len = FFDC_TRACE_ERR_SIZE;
+                break;
+
+            case OCC_SRAM_TRACE_BUF_BASE_INF:
+               l_pTraceLoc = &l_pOccFfdc->iv_occTraceInf[0];
+                setTraceBufAddr (OCC_SRAM_TRACE_BUF_BASE_INF);
+                l_len = FFDC_TRACE_INF_SIZE;
+                break;
+
+            case OCC_SRAM_TRACE_BUF_BASE_IMP:
+                l_pTraceLoc = &l_pOccFfdc->iv_occTraceImp[0];
+                setTraceBufAddr (OCC_SRAM_TRACE_BUF_BASE_IMP);
+                l_len = FFDC_TRACE_IMP_SIZE;
+                break;
+
+            // @TODO will have to collect other OCC SRAM regions once
+            // the util to read and get base + size is done
+
+            default:
+                FAPI_ERR ( "PlatOcc::collectTrace Unknown Address! 0x%08X",
+                           i_sramAddr );
+                // this is likely a code bug, but the overall ffdc flow
+                // must carry on, so we do not break with an error
+                break;
+        }
+
+        if ( l_len != 0 )
+        {
+            FAPI_TRY ( collectSramInfo ( getProcChip(),
+                                         l_pTraceLoc,
+                                         TRACES,
+                                         l_len ),
+                       "::collectTrace Failed Addr: 0x%08X Len: %lu bytes",
+                       i_sramAddr, l_len );
+        }
+
+    fapi_try_exit:
+        FAPI_DBG("<< PlatOcc::collectTrace" );
+        return fapi2::current_err;
+    }
+
+    //--------------------------------------------------------------------------
+
+    fapi2::ReturnCode PlatOcc::updateOccFfdcHeader ( uint8_t * i_pHomerBuf,
+                                                     uint8_t  i_ffdcValid )
+    {
+        FAPI_DBG(">> updateOccFfdcHeader" );
+
+        OccFfdcHeader* l_pOccFfdcHdr = ((OccFfdcHeader*)
+                                       ((OccFfdcHdrRegion*) i_pHomerBuf));
+        l_pOccFfdcHdr->iv_magicWord =  htobe32( FFDC_OCC_MAGIC_NUM );
+        l_pOccFfdcHdr->iv_ffdcValid = i_ffdcValid;
+        l_pOccFfdcHdr->iv_headerSize = sizeof (OccFfdcHeader);
+        l_pOccFfdcHdr->iv_sectionSize = htobe16 (sizeof (OccFfdcRegion));
+        l_pOccFfdcHdr->iv_offsetErrTrace =
+              htobe16 (offsetof (struct OccFfdcRegion, iv_occTraceErr[0]));
+        l_pOccFfdcHdr->iv_offsetImpTrace =
+              htobe16 (offsetof (struct OccFfdcRegion, iv_occTraceImp[0]));
+        l_pOccFfdcHdr->iv_offsetInfTrace =
+              htobe16 (offsetof (struct OccFfdcRegion, iv_occTraceInf[0]));
+        l_pOccFfdcHdr->iv_offsetSsxTrace =
+              htobe16 (offsetof (struct OccFfdcRegion, iv_occTraceSsx[0]));
+        l_pOccFfdcHdr->iv_offsetGpe0Trace =
+              htobe16 (offsetof (struct OccFfdcRegion, iv_occTraceGpe0[0]));
+        l_pOccFfdcHdr->iv_offsetGpe1Trace =
+              htobe16 (offsetof (struct OccFfdcRegion, iv_occTraceGpe1[0]));
+        l_pOccFfdcHdr->iv_offsetSharedSram =
+              htobe16 (offsetof (struct OccFfdcRegion, iv_occSharedSram[0]));
+        l_pOccFfdcHdr->iv_offsetOccRegs =
+              htobe16 (offsetof (struct OccFfdcRegion, iv_occRegs[0]));
+
+        FAPI_DBG( "================== OCC Header ==========================" );
+        FAPI_DBG( "FFDC Validity Vector         :   0x%02x", l_pOccFfdcHdr->iv_ffdcValid );
+        FAPI_DBG( "OCC Header Size              :   0x%02x", l_pOccFfdcHdr->iv_headerSize );
+        FAPI_DBG( "OCC FFDC Section Size        :   0x%04x", REV_2_BYTE(l_pOccFfdcHdr->iv_sectionSize) );
+        FAPI_DBG( "OCC ERR Trace Offset         :   0x%04x", REV_2_BYTE(l_pOccFfdcHdr->iv_offsetErrTrace));
+        FAPI_DBG( "OCC IMP Trace Offset         :   0x%04x", REV_2_BYTE(l_pOccFfdcHdr->iv_offsetImpTrace));
+        FAPI_DBG( "OCC INF Trace Offset         :   0x%04x", REV_2_BYTE(l_pOccFfdcHdr->iv_offsetInfTrace));
+        FAPI_DBG( "OCC SSX Trace Offset         :   0x%04x", REV_2_BYTE(l_pOccFfdcHdr->iv_offsetSsxTrace));
+        FAPI_DBG( "OCC GPE0 Trace Offset        :   0x%04x", REV_2_BYTE(l_pOccFfdcHdr->iv_offsetGpe0Trace));
+        FAPI_DBG( "OCC GPE1 Trace Offset        :   0x%04x", REV_2_BYTE(l_pOccFfdcHdr->iv_offsetGpe1Trace));
+        FAPI_DBG( "OCC Shared SRAM Offset       :   0x%04x", REV_2_BYTE(l_pOccFfdcHdr->iv_offsetSharedSram));
+        FAPI_DBG( "OCC OCC Regs Offset          :   0x%04x", REV_2_BYTE(l_pOccFfdcHdr->iv_offsetOccRegs));
+        FAPI_DBG( "================== OCC Header Ends ====================" );
+
+        FAPI_DBG("<< updateOccFfdcHeader" );
+        return fapi2::FAPI2_RC_SUCCESS;
+    }
+    //--------------------------------------------------------------------------
+
+extern "C"
+{
+    fapi2::ReturnCode p9_pm_recovery_ffdc_occ (
+           const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP >& i_procChip,
+           void*                                               i_pFfdcBuf )
+    {
+        FAPI_DBG (">> p9_pm_recovery_occ" );
+
+        PlatOcc l_occFfdc( i_procChip );
+        FAPI_TRY( l_occFfdc.collectFfdc( i_pFfdcBuf ),
+                  "Failed To Collect OCC FFDC" );
+
+    fapi_try_exit:
+        FAPI_DBG ("<< p9_pm_recovery_occ" );
+        return fapi2::current_err;
+    }
+}
+
+
+}//namespace p9_stop_recov_ffdc ends
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_occ.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_occ.H
new file mode 100644
index 000000000..40ed156ad
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_occ.H
@@ -0,0 +1,91 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_occ.H $ */
+/*                                                                        */
+/* OpenPOWER HostBoot Project                                             */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __PM_RECOVERY_FFDC_OCC_
+#define __PM_RECOVERY_FFDC_OCC_
+
+///
+/// @file   p9_pm_recovery_ffdc_occ.H
+/// @brief  Models OCC platform for the FFDC collection of PM complex
+///
+/// *HWP HWP Owner:      Greg Still <stillgs@us.ibm.com>
+/// *HWP FW Owner:       Amit Tendolkar <amit.tendolkar@in.ibm.com>
+/// *HWP Team:           PM
+/// *HWP Level:          2
+/// *HWP Consumed by:    Hostboot
+//
+// *INDENT-OFF*
+//--------------------------------------------------------------------------
+// Includes
+//--------------------------------------------------------------------------
+#include <fapi2.H>
+#include <stdint.h>
+#include <p9_pm_recovery_ffdc_base.H>
+
+namespace p9_stop_recov_ffdc
+{
+
+    class PlatOcc : public PlatPmComplex
+    {
+            public:
+            /// @brief  constructor
+            PlatOcc ( const fapi2::Target <fapi2::TARGET_TYPE_PROC_CHIP>
+                      i_procChipTgt );
+
+            /// @brief  destructor
+            virtual ~PlatOcc() { };
+
+            /// @brief      collects FFDC of the OCC 405, GPE0 and GPE1.
+            /// @param[in]  i_pHomerBuf     points to base of P9 HOMER.
+            /// @return     fapi2 return code.
+            fapi2::ReturnCode collectFfdc( void* i_pHomerBuf );
+
+        private:
+            /// @brief      collects trace info from OCC SRAM buffer.
+            /// @param[in]  i_pHomerBuf     location in HOMER to write at
+            /// @param[in]  i_sramAddress   location in OCC SRAM to read from
+            /// @return     fapi2 return code.
+            fapi2::ReturnCode  collectTrace( uint8_t * i_pHomerBuf,
+                                             uint32_t  i_sramAddress );
+
+            /// @brief updates the OCC FFDC Header
+            /// @param[in]   i_pHomerBuf points to a location in HOMER meant for
+            ///                          OCC FFDC Header
+            ///@param[in]   i_ffdcValid  Indicates what fields in OCC FFDC are
+            ///                          valid. See OccFfdcValidStatus
+            ///@return      fapi2 return code.
+            fapi2::ReturnCode updateOccFfdcHeader ( uint8_t* i_pHomerBuf,
+                                                    uint8_t  i_ffdcValid );
+    };
+
+extern "C"
+{
+    typedef fapi2::ReturnCode( *p9_pm_recovery_ffdc_occ_FP_t )
+            ( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_procChipTgt,
+              void* i_occFfdcBuf );
+}
+
+} //namespace p9_stop_recov_ffdc ends
+
+#endif //__PM_RECOVERY_FFDC_OCC_
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_occ.mk b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_occ.mk
new file mode 100644
index 000000000..4b7058e1b
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_occ.mk
@@ -0,0 +1,32 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_occ.mk $
+#
+# OpenPOWER HostBoot Project
+#
+# Contributors Listed Below - COPYRIGHT 2017
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+PROCEDURE=p9_pm_recovery_ffdc_occ
+PM_FFDC_INC=$(ROOTPATH)/chips/p9/procedures/hwp/pm/
+PM_FFDC_INC+=$(ROOTPATH)/chips/p9/procedures/hwp/lib
+lib$(PROCEDURE)_DEPLIBS +=p9_pm_recovery_ffdc_base
+lib$(PROCEDURE)_DEPLIBS+=p9_pm_ocb_indir_access
+lib$(PROCEDURE)_DEPLIBS+=p9_pm_ocb_indir_setup_linear
+$(call ADD_MODULE_INCDIR,$(PM_FFDC_INC))
+$(call BUILD_PROCEDURE)
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_sgpe.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_sgpe.C
index 15376c5f5..d79472f4a 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_sgpe.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_sgpe.C
@@ -42,6 +42,7 @@
 
 #include <p9_pm_recovery_ffdc_sgpe.H>
 #include <p9_hcd_memmap_occ_sram.H>
+#include <p9_ppe_defs.H>
 #include <stddef.h>
 #include <endian.h>
 
@@ -63,7 +64,7 @@
         fapi2::ReturnCode l_retCode = fapi2::FAPI2_RC_SUCCESS;
         uint8_t l_ffdcValdityVect = PPE_FFDC_ALL_VALID;
 
-        uint8_t l_haltState = 0; //FIXME Needs update when PPE State gets handled
+        uint8_t l_haltState = PPE_HALT_COND_UNKNOWN;
         uint8_t *l_pFfdcLoc = NULL;
 
         HomerFfdcRegion * l_pHomerFfdc =
@@ -72,6 +73,14 @@
         l_pFfdcLoc = (uint8_t *)(&l_pHomerFfdc->iv_sgpeFfdcRegion);
 
         //In case of error , invalidate FFDC in header.
+        l_retCode = collectPpeState ( SGPE_BASE_ADDRESS, l_pFfdcLoc );
+        if ( l_retCode != fapi2::FAPI2_RC_SUCCESS )
+        {
+            FAPI_ERR ( "Error collecting SGPE State" );
+            // PPE State Data is bad & continue SRAM FFDC collection
+            l_ffdcValdityVect &= ~PPE_STATE_VALID;
+        }
+
         l_retCode = collectTrace( l_pFfdcLoc );
 
         if( l_retCode )
@@ -149,13 +158,6 @@
 
     //-----------------------------------------------------------------------
 
-    fapi2::ReturnCode  PlatSgpe::collectSgpeState( uint8_t * i_pSgpeState )
-    {
-        return fapi2::FAPI2_RC_SUCCESS;
-    }
-
-    //-----------------------------------------------------------------------
-
     fapi2::ReturnCode PlatSgpe::collectInternalReg( uint8_t * i_pSgpeIntReg )
     {
         return fapi2::FAPI2_RC_SUCCESS;
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_sgpe.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_sgpe.H
index 5bb96965c..227a1f188 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_sgpe.H
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_sgpe.H
@@ -71,11 +71,6 @@ namespace p9_stop_recov_ffdc
             /// @return     fapi2 return code.
             fapi2::ReturnCode  collectGlobals( uint8_t * i_pHomerBuf );
 
-            /// @brief      collects SGPE state
-            /// @param[in]  i_pHomerBuf     points to location of HOMER meant for SGPE's state.
-            /// @return     fapi2 return code.
-            fapi2::ReturnCode  collectSgpeState( uint8_t * i_pHomerBuf );
-
             /// @brief      collects internal register info for a SGPE
             /// @param[in]  i_pHomerBuf     points to location of HOMER meant for SGPE internal register.
             /// @return     fapi2 return code.