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author | Greg Still <stillgs@us.ibm.com> | 2018-01-25 21:15:47 -0600 |
---|---|---|
committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2018-02-17 16:26:51 -0500 |
commit | 54a8d9a839e8127991e5b582045d1a44ea526007 (patch) | |
tree | 6a620b918fd89873766b44cd525d6f98ade4ae62 /src/import | |
parent | b542fd6392999e7d521c5dff5a2a2add056db984 (diff) | |
download | talos-hostboot-54a8d9a839e8127991e5b582045d1a44ea526007.tar.gz talos-hostboot-54a8d9a839e8127991e5b582045d1a44ea526007.zip |
PM: Use auto-special wake-up to cover PM complex reset window
- Removes SGPE Activity checking in Special Wake-up
- Added LMCR scom error check
- Fixed some bugs in lmcr check
CQ: SW412666
CMVC-Prereq: 1045635
Change-Id: I10948635f3f3b26fe4d9d38f79e13c09a290140a
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52690
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52696
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import')
6 files changed, 214 insertions, 20 deletions
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_cpu_special_wakeup_core.C b/src/import/chips/p9/procedures/hwp/pm/p9_cpu_special_wakeup_core.C index 56349e46d..793996e41 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_cpu_special_wakeup_core.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_cpu_special_wakeup_core.C @@ -40,6 +40,8 @@ #include <p9_cpu_special_wakeup_lib.H> #include <p9_ppe_defs.H> #include <p9_ppe_utils.H> +#include <p9n2_quad_scom_addresses.H> +#include <p9n2_quad_scom_addresses_fld.H> fapi2::ReturnCode collectCoreTimeoutFailInfo( const fapi2::Target < fapi2::TARGET_TYPE_CORE>& i_target, ProcessingValues_t i_processing_info ); @@ -59,9 +61,22 @@ fapi2::ReturnCode p9_cpu_special_wakeup_core( { FAPI_INF(">> p9_cpu_special_wakeup_core"); fapi2::ReturnCode l_rc; - uint8_t l_spWakeUpInProg = 0; + fapi2::buffer<uint64_t> l_cpmmrRegVal; + fapi2::buffer<uint64_t> l_lmcrRegVal; + uint8_t l_spWakeUpInProg = 0; + uint8_t l_corePos = 0; + uint8_t l_autoSplWkUpBitPos = 12; //EQ_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE + uint8_t l_lmcr_fail_state = 0; + ProcessingValues_t l_processing_info; auto l_eqTarget = i_target.getParent<fapi2::TARGET_TYPE_EQ>(); + auto l_exTarget = i_target.getParent<fapi2::TARGET_TYPE_EX>(); + + FAPI_ATTR_GET( fapi2::ATTR_CHIP_UNIT_POS, + i_target, + l_corePos ); + + l_autoSplWkUpBitPos = l_autoSplWkUpBitPos + ( l_corePos & 0x01) ; FAPI_ATTR_GET( fapi2::ATTR_CORE_INSIDE_SPECIAL_WAKEUP, i_target, @@ -80,6 +95,44 @@ fapi2::ReturnCode p9_cpu_special_wakeup_core( p9specialWakeup::blockWakeupRecurssion( l_eqTarget, p9specialWakeup::BLOCK ); + //Not using FAPI TRY to avoid chances of RC corruption + l_rc = getScom( i_target, P9N2_C_CPPM_CPMMR_SCOM, l_cpmmrRegVal ); + + if( l_rc ) + { + FAPI_ERR("Failed to SCOM CPMMR Reg, Core Pos %d", l_corePos ); + return l_rc; + } + + l_rc = getScom( l_exTarget, EX_CME_SCOM_LMCR_SCOM, l_lmcrRegVal ); + + + if( (l_rc) && (l_rc != (uint32_t)PIB_CHIPLET_OFFLINE_ERR )) + { + FAPI_ERR("Failed to SCOM LMCR Reg, EX Pos %d", (l_corePos >> 1 ) ); + return l_rc; + } + else if ((l_rc) && (l_rc == (uint32_t)PIB_CHIPLET_OFFLINE_ERR )) + { + l_rc = fapi2::FAPI2_RC_SUCCESS; + l_lmcr_fail_state = 1; + } + + if( !l_lmcrRegVal.getBit( l_autoSplWkUpBitPos ) && + !l_lmcr_fail_state) + { + if( l_cpmmrRegVal.getBit( P9N2_EX_CPPM_CPMMR_WKUP_NOTIFY_SELECT ) ) + { + //If auto special wakeup is enabled and Special wakeup signal is not + //getting routed towards CME, let us route it towards CME so that + //CME HW asserts DONE bit without CME Firmware's intervention. + FAPI_DBG("Enabling Auto Special Wakeup For Core %d", l_corePos ); + + l_cpmmrRegVal.clearBit( P9N2_EX_CPPM_CPMMR_WKUP_NOTIFY_SELECT ); + putScom( i_target, P9N2_C_CPPM_CPMMR_SCOM, l_cpmmrRegVal ); + } + } + l_rc = _special_wakeup<fapi2::TARGET_TYPE_CORE> ( i_target, i_operation, diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_cpu_special_wakeup_ex.C b/src/import/chips/p9/procedures/hwp/pm/p9_cpu_special_wakeup_ex.C index 768c28c3c..b7016bcd4 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_cpu_special_wakeup_ex.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_cpu_special_wakeup_ex.C @@ -40,6 +40,8 @@ #include <p9_cpu_special_wakeup_lib.H> #include <p9_ppe_defs.H> #include <p9_ppe_utils.H> +#include <p9n2_quad_scom_addresses.H> +#include <p9n2_quad_scom_addresses_fld.H> fapi2::ReturnCode collectExTimeoutFailInfo( const fapi2::Target < fapi2::TARGET_TYPE_EX>& i_target, ProcessingValues_t i_processing_info ); @@ -60,7 +62,13 @@ fapi2::ReturnCode p9_cpu_special_wakeup_ex( fapi2::ReturnCode l_rc; ProcessingValues_t l_processing_info; uint8_t l_spWakeUpInProg = 0; + fapi2::buffer<uint64_t> l_cpmmrRegVal; + fapi2::buffer<uint64_t> l_lmcrRegVal; + uint8_t l_autoSplWkUpBitPos = 12; //EQ_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE + uint8_t l_corePos = 0; auto l_eqTarget = i_target.getParent<fapi2::TARGET_TYPE_EQ>(); + auto l_coreList = i_target.getChildren<fapi2::TARGET_TYPE_CORE>( ); + uint8_t l_lmcr_fail_state = 0; FAPI_ATTR_GET( fapi2::ATTR_EX_INSIDE_SPECIAL_WAKEUP, i_target, @@ -79,6 +87,56 @@ fapi2::ReturnCode p9_cpu_special_wakeup_ex( p9specialWakeup::blockWakeupRecurssion( l_eqTarget, p9specialWakeup::BLOCK ); + //Not using FAPI TRY to avoid chances of RC corruption + l_rc = getScom( i_target, EX_CME_SCOM_LMCR_SCOM, l_lmcrRegVal ); + + + if( (l_rc) && (l_rc != (uint32_t)PIB_CHIPLET_OFFLINE_ERR )) + { + FAPI_ERR("Failed to SCOM LMCR Reg, EX Pos %d", (l_corePos >> 1 ) ); + return l_rc; + } + else if ((l_rc) && (l_rc == (uint32_t)PIB_CHIPLET_OFFLINE_ERR )) + { + l_rc = fapi2::FAPI2_RC_SUCCESS; + l_lmcr_fail_state = 1; + } + + + if (!l_lmcr_fail_state) + { + for( auto l_core : l_coreList ) + { + FAPI_ATTR_GET( fapi2::ATTR_CHIP_UNIT_POS, + l_core, + l_corePos ); + + l_autoSplWkUpBitPos = l_autoSplWkUpBitPos + ( l_corePos & 0x01) ; + + l_rc = getScom( l_core, P9N2_C_CPPM_CPMMR_SCOM, l_cpmmrRegVal ); + + if( l_rc ) + { + FAPI_ERR("Failed to SCOM CPMMR Reg, Core Pos %d", l_corePos ); + return l_rc; + } + + if( !l_lmcrRegVal.getBit( l_autoSplWkUpBitPos ) ) + { + if( l_cpmmrRegVal.getBit( P9N2_EX_CPPM_CPMMR_WKUP_NOTIFY_SELECT ) ) + { + //If auto special wakeup is enabled and Special wakeup signal is not + //getting routed towards CME, let us route it towards CME so that + //CME HW asserts DONE bit without CME Firmware's intervention. + + FAPI_DBG("Enabling Auto Special Wakeup For Core %d", l_corePos ); + l_cpmmrRegVal.clearBit( P9N2_EX_CPPM_CPMMR_WKUP_NOTIFY_SELECT ); + putScom( l_core, P9N2_C_CPPM_CPMMR_SCOM, l_cpmmrRegVal ); + } + } + } + } + l_rc = _special_wakeup( i_target, i_operation, i_entity, diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_cpu_special_wakeup_lib.H b/src/import/chips/p9/procedures/hwp/pm/p9_cpu_special_wakeup_lib.H index 3283c73bf..3ee14e267 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_cpu_special_wakeup_lib.H +++ b/src/import/chips/p9/procedures/hwp/pm/p9_cpu_special_wakeup_lib.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -45,6 +45,7 @@ static const uint32_t NUM_CHIPLET_TYPES = 2; static const uint32_t NUM_ENTITIES = 4; +#define PIB_CHIPLET_OFFLINE_ERR 0x2 /** @@ -670,20 +671,6 @@ fapi2::ReturnCode _special_wakeup(const fapi2::Target<K>& i_chipletTarget, { case p9specialWakeup::SPCWKUP_ENABLE: - // Check if PM subsystem is ready for SPW - // Moved under wakeup enable, because always want to let - // SPW to be cleared - FAPI_TRY(fapi2::getScom(l_parentTarget, - PU_OCB_OCI_OCCFLG_SCOM, - occFlagReg), - "GetScom of OCC Flag Register Failed"); - - if( !occFlagReg.getBit<SGPE_ACTIVE_BIT>() ) - { - FAPI_INF("SGPE not active. STOP Sub-System not ready for special wakeup" ); - break; - } - // Select the addresses to use based on the entity FAPI_TRY(spwkup_setup_entity(i_chipletTarget, i_entity, io_processing_values), "Error: spwkup_setup_entity failed"); diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.C index 4c633c0bc..30b5d8342 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.C @@ -120,6 +120,11 @@ fapi2::ReturnCode p9_pm_reset( FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After EX in special wakeup")); // ************************************************************************ + // Enable the Auto Special Wake-up Function on all EXs + // ************************************************************************ + FAPI_TRY(p9_pm_set_auto_spwkup(i_target)); + + // ************************************************************************ // Mask the PBA & CME FIRs as errors can occur in what follows // ************************************************************************ FAPI_DBG("Executing p9_pm_firinit for masking errors in reset operation."); @@ -376,3 +381,64 @@ p9_pm_reset_psafe_update(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_ta fapi_try_exit: return fapi2::current_err; } + +// Walk through each EX chiplet (and each core within an EX) to determine if +// special wake-up done is asserted. If so, set auto special wake-up mode to +// protect the core(s) while the PM complex is being reset. + +fapi2::ReturnCode +p9_pm_set_auto_spwkup(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) +{ + + FAPI_INF(">> p9_set_auto_spwkup"); + + // For each EX target + for (auto& l_ex_chplt : i_target.getChildren<fapi2::TARGET_TYPE_EX> + (fapi2::TARGET_STATE_FUNCTIONAL)) + { + + fapi2::buffer<uint64_t> l_gpmmr; + fapi2::buffer<uint64_t> l_lmcr; + uint32_t l_bit; + + fapi2::ATTR_CHIP_UNIT_POS_Type l_ex_num; + FAPI_TRY(FAPI_ATTR_GET( fapi2::ATTR_CHIP_UNIT_POS, + l_ex_chplt, + l_ex_num)); + + for (auto& l_core : l_ex_chplt.getChildren<fapi2::TARGET_TYPE_CORE> + (fapi2::TARGET_STATE_FUNCTIONAL)) + { + fapi2::ATTR_CHIP_UNIT_POS_Type l_core_num; + FAPI_TRY(FAPI_ATTR_GET( fapi2::ATTR_CHIP_UNIT_POS, + l_core, + l_core_num)); + FAPI_DBG("Checking for special wakeup done on core %d in EX %d ", + l_core_num, l_ex_num); + + FAPI_TRY(fapi2::getScom(l_core, C_PPM_GPMMR_SCOM, l_gpmmr), + "GetScom of GPMMR failed"); + + if (l_gpmmr.getBit<EQ_PPM_GPMMR_SPECIAL_WKUP_DONE>()) + { + // Clear the auto special wake-up disable (eg enable it) for the core + l_bit = EQ_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE + (l_core_num % 2); + l_lmcr.flush<0>().setBit(l_bit); + FAPI_TRY(fapi2::putScom(l_ex_chplt, EX_CME_SCOM_LMCR_SCOM1, l_lmcr), + "PutScom of LMCR failed"); + } + else + { + FAPI_ASSERT (false, + fapi2::PM_RESET_SPWKUP_DONE_ERROR() + .set_CORE_TARGET(l_core) + .set_GPMMR(l_gpmmr), + "Core expected to be in special wake-up is not prior to setting auto special wake-up mode"); + } + } + } + +fapi_try_exit: + FAPI_INF("<< p9_set_auto_spwkup"); + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.H index 5bfc20324..f4e8ad6d0 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.H +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -88,8 +88,23 @@ extern "C" /// @param[in] i_target Proc Chip target /// /// @return FAPI2_RC_SUCCESS on success, else error code. - fapi2::ReturnCode p9_pm_reset_psafe_update - (const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); + fapi2::ReturnCode p9_pm_reset_psafe_update( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); + +//------------------------------------------------------------------------------ +/// +/// @brief Walk through each EX chiplet (and each core within an EX) to determine +/// if special wake-up done is asserted. If so, set auto special wake-up mode to +/// protect the core(s) while the PM complex is being reset +/// +/// @param[in] i_target Proc Chip target +/// +/// @return FAPI2_RC_SUCCESS on success, else error code. + fapi2::ReturnCode p9_pm_set_auto_spwkup( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); + + + } #endif // _P9_PM_RESET_H diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_pm_init_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_pm_init_errors.xml index 5998f16de..97edba0e8 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_pm_init_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_pm_init_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2016,2017 --> +<!-- Contributors Listed Below - COPYRIGHT 2016,2018 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -89,4 +89,19 @@ <priority>HIGH</priority> </callout> </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_PM_RESET_SPWKUP_DONE_ERROR</rc> + <description>Core expected to be in special wake-up is not prior to setting + auto special wake-up mode + </description> + <ffdc>CORE_TARGET</ffdc> + <ffdc>DPLL_FREQ</ffdc> + <ffdc>GPMMR</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + <!-- ******************************************************************** --> </hwpErrors> |