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| author | Mike Baiocchi <mbaiocch@us.ibm.com> | 2017-05-30 07:40:20 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-06-07 09:38:48 -0400 |
| commit | 449f2ba22f199b36de5e041ff8d028af8c3c3652 (patch) | |
| tree | eea0511f751a5ec9c6fe924735c588217e08b4e6 /src/import | |
| parent | 348f773c8691b2d074411c741a048e6f08cd887e (diff) | |
| download | talos-hostboot-449f2ba22f199b36de5e041ff8d028af8c3c3652.tar.gz talos-hostboot-449f2ba22f199b36de5e041ff8d028af8c3c3652.zip | |
Check Scratch Register 3 bit 7 and set new ATTR_SECURE_SETTINGS
Change-Id: Ia125ce6fdf5a15acf30a11e3124fae86c645d96c
RTC:163094
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41107
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Marshall J. Wilks <mjwilks@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-by: Stephen M. Cprek <smcprek@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41111
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src/import')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H index bb2020815..00587c31f 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H +++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H @@ -59,6 +59,20 @@ enum SbeBootloaderVersion MMIO_BARS_ADDED = 0x00090003, }; +union BootloaderSecureSettings +{ + uint8_t data8; + struct + { + // Bit Breakdown - sync with ATTR_SECURE_SETTINGS + uint8_t reserved : 5; // reserved + uint8_t allowAttrOverrides : 1; // Allow Attribute Overrides in + // Secure Mode + uint8_t securityOverride : 1; // Security Override + uint8_t secureAccessBit : 1; // Secure Access Bit + } __attribute__((packed)); +}; + // Structure starts at the bootloader zero address struct BootloaderConfigData_t { @@ -67,7 +81,7 @@ struct BootloaderConfigData_t uint8_t pnorBootSide; // byte 9 0=PNOR side A, 1=PNOR side B [ATTR_PNOR_BOOT_SIDE] uint16_t pnorSizeMB; // bytes 10:11 Size of PNOR in MB [ATTR_PNOR_SIZE] uint64_t blLoadSize; // bytes 12:19 Size of Load (Exception vectors and Bootloader) - uint8_t secureAccessBit; // byte 20 + BootloaderSecureSettings secureSettings ; // byte 20 uint64_t xscomBAR; // bytes 21:28 XSCOM MMIO BAR uint64_t lpcBAR; // bytes 29:36 LPC MMIO BAR }; |
