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authorJohn Rell <jgrell@us.ibm.com>2017-06-14 19:35:24 -0500
committerChristian R. Geddes <crgeddes@us.ibm.com>2017-07-06 08:34:44 -0400
commit197ae322af1636b5a146fd46b3575165fbbbc2d5 (patch)
tree21920c3b9ff040d1e5185aa798656a837ea43b63 /src/import
parentf0e3f6dfcbec36f0fdf631172f973209ff645bc1 (diff)
downloadtalos-hostboot-197ae322af1636b5a146fd46b3575165fbbbc2d5.tar.gz
talos-hostboot-197ae322af1636b5a146fd46b3575165fbbbc2d5.zip
jgr17061400 Adding setting for Nim DD2
Also updated scominit.C to enable target 2 for g0 file Change-Id: I521395389e353185c82df0c01a662a386f370bd2 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41864 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Richard J. Knight <rjknight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41865 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import')
-rw-r--r--src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g0_scom.C24
-rw-r--r--src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g0_scom.H6
-rw-r--r--src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g1_scom.C18
-rw-r--r--src/import/chips/p9/procedures/hwp/io/p9_io_xbus_scominit.C4
4 files changed, 46 insertions, 6 deletions
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g0_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g0_scom.C
index 4b40d7421..a73de3f94 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g0_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g0_scom.C
@@ -60,13 +60,19 @@ constexpr uint64_t literal_0b1100 = 0b1100;
constexpr uint64_t literal_0b00 = 0b00;
fapi2::ReturnCode p9_xbus_g0_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>& TGT0,
- const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1)
+ const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1, const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& TGT2)
{
{
+ fapi2::ATTR_EC_Type l_chip_ec;
+ fapi2::ATTR_NAME_Type l_chip_id;
+ FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_NAME, TGT2, l_chip_id));
+ FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_EC, TGT2, l_chip_ec));
fapi2::ATTR_IS_SIMULATION_Type l_TGT1_ATTR_IS_SIMULATION;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, TGT1, l_TGT1_ATTR_IS_SIMULATION));
uint64_t l_def_IS_HW = (l_TGT1_ATTR_IS_SIMULATION == literal_0);
uint64_t l_def_IS_SIM = (l_TGT1_ATTR_IS_SIMULATION == literal_1);
+ fapi2::ATTR_CHIP_EC_FEATURE_HW393297_Type l_TGT2_ATTR_CHIP_EC_FEATURE_HW393297;
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW393297, TGT2, l_TGT2_ATTR_CHIP_EC_FEATURE_HW393297));
fapi2::ATTR_IO_XBUS_MASTER_MODE_Type l_TGT0_ATTR_IO_XBUS_MASTER_MODE;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IO_XBUS_MASTER_MODE, TGT0, l_TGT0_ATTR_IO_XBUS_MASTER_MODE));
uint64_t l_def_is_master = (l_TGT0_ATTR_IO_XBUS_MASTER_MODE == literal_1);
@@ -2954,6 +2960,22 @@ fapi2::ReturnCode p9_xbus_g0_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>&
FAPI_TRY(fapi2::putScom(TGT0, 0x8004441006010c3full, l_scom_buffer));
}
{
+ FAPI_TRY(fapi2::getScom( TGT0, 0x8008000006010c3full, l_scom_buffer ));
+
+ if ((l_TGT2_ATTR_CHIP_EC_FEATURE_HW393297 == literal_0))
+ {
+ constexpr auto l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PG_SPARE_MODE_0_ON = 0x1;
+ l_scom_buffer.insert<48, 1, 63, uint64_t>(l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PG_SPARE_MODE_0_ON );
+ }
+ else if (( true ))
+ {
+ constexpr auto l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PG_SPARE_MODE_0_OFF = 0x0;
+ l_scom_buffer.insert<48, 1, 63, uint64_t>(l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PG_SPARE_MODE_0_OFF );
+ }
+
+ FAPI_TRY(fapi2::putScom(TGT0, 0x8008000006010c3full, l_scom_buffer));
+ }
+ {
FAPI_TRY(fapi2::getScom( TGT0, 0x8008080006010c3full, l_scom_buffer ));
l_scom_buffer.insert<48, 6, 58, uint64_t>(literal_0b000000 );
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g0_scom.H b/src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g0_scom.H
index dea3afdc4..ecf5f7238 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g0_scom.H
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g0_scom.H
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2016 */
+/* Contributors Listed Below - COPYRIGHT 2016,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -32,13 +32,13 @@
typedef fapi2::ReturnCode (*p9_xbus_g0_scom_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>&,
- const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>&);
+ const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>&, const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
extern "C"
{
fapi2::ReturnCode p9_xbus_g0_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>& TGT0,
- const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1);
+ const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1, const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& TGT2);
}
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g1_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g1_scom.C
index c63ab9979..6932f6e7b 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g1_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g1_scom.C
@@ -72,6 +72,8 @@ fapi2::ReturnCode p9_xbus_g1_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>&
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, TGT1, l_TGT1_ATTR_IS_SIMULATION));
uint64_t l_def_IS_HW = (l_TGT1_ATTR_IS_SIMULATION == literal_0);
uint64_t l_def_IS_SIM = (l_TGT1_ATTR_IS_SIMULATION == literal_1);
+ fapi2::ATTR_CHIP_EC_FEATURE_HW393297_Type l_TGT2_ATTR_CHIP_EC_FEATURE_HW393297;
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW393297, TGT2, l_TGT2_ATTR_CHIP_EC_FEATURE_HW393297));
fapi2::ATTR_IO_XBUS_MASTER_MODE_Type l_TGT0_ATTR_IO_XBUS_MASTER_MODE;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IO_XBUS_MASTER_MODE, TGT0, l_TGT0_ATTR_IO_XBUS_MASTER_MODE));
uint64_t l_def_is_master = (l_TGT0_ATTR_IO_XBUS_MASTER_MODE == literal_1);
@@ -2959,6 +2961,22 @@ fapi2::ReturnCode p9_xbus_g1_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>&
FAPI_TRY(fapi2::putScom(TGT0, 0x8004443006010c3full, l_scom_buffer));
}
{
+ FAPI_TRY(fapi2::getScom( TGT0, 0x8008002006010c3full, l_scom_buffer ));
+
+ if ((l_TGT2_ATTR_CHIP_EC_FEATURE_HW393297 == literal_0))
+ {
+ constexpr auto l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PG_SPARE_MODE_0_ON = 0x1;
+ l_scom_buffer.insert<48, 1, 63, uint64_t>(l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PG_SPARE_MODE_0_ON );
+ }
+ else if (( true ))
+ {
+ constexpr auto l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PG_SPARE_MODE_0_OFF = 0x0;
+ l_scom_buffer.insert<48, 1, 63, uint64_t>(l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PG_SPARE_MODE_0_OFF );
+ }
+
+ FAPI_TRY(fapi2::putScom(TGT0, 0x8008002006010c3full, l_scom_buffer));
+ }
+ {
FAPI_TRY(fapi2::getScom( TGT0, 0x8008082006010c3full, l_scom_buffer ));
l_scom_buffer.insert<48, 6, 58, uint64_t>(literal_0b000001 );
diff --git a/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_scominit.C b/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_scominit.C
index 690b9f272..771e87b33 100644
--- a/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_scominit.C
+++ b/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_scominit.C
@@ -170,7 +170,7 @@ fapi2::ReturnCode p9_io_xbus_scominit(
{
case ENUM_ATTR_XBUS_GROUP_0:
FAPI_INF("Group 0:Invoke FAPI procedure core: input_target");
- FAPI_EXEC_HWP(rc, p9_xbus_g0_scom, i_target, l_system_target);
+ FAPI_EXEC_HWP(rc, p9_xbus_g0_scom, i_target, l_system_target, l_proc);
if( rc )
{
@@ -180,7 +180,7 @@ fapi2::ReturnCode p9_io_xbus_scominit(
}
FAPI_INF("Group 0:Invoke FAPI procedure core: connected_target");
- FAPI_EXEC_HWP(rc, p9_xbus_g0_scom, i_connected_target, l_system_target);
+ FAPI_EXEC_HWP(rc, p9_xbus_g0_scom, i_connected_target, l_system_target, l_proc);
if( rc )
{
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