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| author | Prem Shanker Jha <premjha2@in.ibm.com> | 2017-08-14 05:04:38 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-09-29 15:05:40 -0400 |
| commit | 18f1765b8bfff41826f129926b8a6d18509d1de2 (patch) | |
| tree | d184e85148d883ab6089ad1173c96e8beb4714cf /src/import | |
| parent | b0d5f27a21da630c3eb9072692e7b72cff134d2e (diff) | |
| download | talos-hostboot-18f1765b8bfff41826f129926b8a6d18509d1de2.tar.gz talos-hostboot-18f1765b8bfff41826f129926b8a6d18509d1de2.zip | |
PM: Change in logic for PGPE SRAM image size check.
Commit updates the logic for PGPE SRAM image size check.
PGPE Hcode and Global P-State Parameter Block together
should not exceed 44KB. Following is the distribution
for PGPE region of OCC SRAM
- PGPE Hcode + GPSPB : 44KB
- PGPE Aux Task : 2KB
- PGPE Boot Loader : 1KB
- PPMR Header : 1KB
Change-Id: I47b033497b6815909c6d183823d09806ef77f375
RTC: 178482
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44582
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Juan R. Medina <jrmedina@us.ibm.com>
Reviewed-by: RAHUL BATRA <rbatra@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44583
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import')
4 files changed, 27 insertions, 8 deletions
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H index dd98d54b5..6cb5ed06c 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H @@ -79,6 +79,7 @@ HCD_CONST(TWO_MB, (2 * 1024 * 1024)) HCD_CONST(CME_SRAM_SIZE, (32 * ONE_KB)) HCD_CONST(OCC_SRAM_SIZE, (768 * ONE_KB)) +HCD_CONST(PGPE_IMAGE_SIZE, (44 * ONE_KB)) HCD_CONST(HOMER_MEMORY_SIZE, (4 * ONE_MB)) HCD_CONST(HOMER_OPMR_REGION_NUM, 0) @@ -422,7 +423,7 @@ HCD_CONST(CPMR_DEBUG_REGION_SIZE, (64 * ONE_KB)) // 192K + 64K = 2 /// PPMR Header HCD_CONST(PPMR_HOMER_OFFSET, (HOMER_PPMR_REGION_NUM* ONE_MB)) -HCD_CONST(PPMR_HEADER_SIZE, 512) +HCD_CONST(PPMR_HEADER_SIZE, 1024) HCD_CONST(PPMR_MAGIC_NUMBER_BYTE, 0x00) HCD_CONST(PPMR_BOOT_COPIER_OFFSET_BYTE, 0x08) @@ -460,7 +461,7 @@ HCD_CONST(PGPE_INSTRUMENTATION_SIZE, (2 * ONE_KB)) HCD_CONST(PGPE_AUX_TASK_SIZE, (2 * ONE_KB)) HCD_CONST(PGPE_IMAGE_PPMR_OFFSET, (PGPE_BOOT_LOADER_PPMR_OFFSET + PGPE_BOOT_LOADER_SIZE)) -HCD_CONST(PGPE_IMAGE_SIZE, (48 * ONE_KB)) //RTC158543 +HCD_CONST(PGPE_HCODE_SIZE, (40 * ONE_KB)) // PGPE Img + GPPB HCD_CONST(PGPE_INT_VECTOR_SIZE, 384) HCD_CONST(PGPE_HCODE_RESET_ADDR_VAL, 0x40) diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H index 67733867e..f890a93c3 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H @@ -51,7 +51,7 @@ HCD_CONST(OCC_SRAM_BASE_ADDR, 0xFFF00000) HCD_CONST(OCC_SRAM_IPC_REGION_SIZE, (4 * ONE_KB)) HCD_CONST(OCC_SRAM_GPE0_REGION_SIZE, (60 * ONE_KB)) HCD_CONST(OCC_SRAM_GPE1_REGION_SIZE, (64 * ONE_KB)) -HCD_CONST(OCC_SRAM_PGPE_REGION_SIZE, PGPE_IMAGE_SIZE) +HCD_CONST(OCC_SRAM_PGPE_REGION_SIZE, (48 * ONE_KB )) HCD_CONST(OCC_SRAM_SGPE_REGION_SIZE, SGPE_IMAGE_SIZE) HCD_CONST(OCC_SRAM_OCC_REGION_SIZE, (512 * ONE_KB)) diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C index d2158cff7..66f16d637 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C @@ -283,12 +283,12 @@ ImgSizeBank::ImgSizeBank() iv_secSize[ImgSec(PLAT_CME, P9_XIP_SECTION_CME_HCODE, (char*)"CME Hcode")] = CME_SRAM_SIZE; iv_secSize[ImgSec(PLAT_CME, CME_SRAM_IMAGE, (char*)"CME SRAM Image")] = CME_SRAM_SIZE; - iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_PPMR, (char*)"PPMR Header")] = HALF_KB; + iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_PPMR, (char*)"PPMR Header")] = ONE_KB; iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_LVL1_BL, (char*)"PGPE Boot Copier")] = PGPE_BOOT_COPIER_SIZE; iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_LVL2_BL, (char*)"PGPE Boot Loader")] = PGPE_BOOT_LOADER_SIZE;; - iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_HCODE, (char*)"PGPE Hcode")] = PGPE_IMAGE_SIZE; + iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_HCODE, (char*)"PGPE Hcode")] = PGPE_HCODE_SIZE; iv_secSize[ImgSec(PLAT_PGPE, PGPE_SRAM_IMAGE, (char*)"PGPE SRAM Image")] = PGPE_IMAGE_SIZE; - iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_AUX_TASK, (char*)"PGPE Aux Task")] = PGPE_AUX_TASK_SIZE; + iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_AUX_TASK, (char*)"PGPE Aux Task")] = PGPE_AUX_TASK_SIZE; } /** @@ -321,7 +321,8 @@ uint32_t ImgSizeBank::isSizeGood( PlatId i_plat, uint8_t i_sec, break; } - if( i_size > tempSize ) + //if size is either zero or greater than max size allowed, return max size allowed. + if( ( 0 == i_size ) || ( i_size > tempSize ) ) { rc = tempSize; // returning Max Allowed size as return code break; @@ -1666,7 +1667,9 @@ fapi2::ReturnCode buildPgpeImage( void* const i_pImageIn, Homerlayout_t* i_pChip i_procFuncModel.getChipLevel(), ppeSection ); - io_ppmrHdr.g_ppmr_aux_task_offset = io_ppmrHdr.g_ppmr_aux_task_offset + PGPE_AUX_TASK_SIZE; + //FIXME RTC 178555 Add size check for PGPE Auxiliary Task binary. + + io_ppmrHdr.g_ppmr_aux_task_offset = io_ppmrHdr.g_ppmr_hcode_offset + PGPE_IMAGE_SIZE; io_ppmrHdr.g_ppmr_aux_task_length = ppeSection.iv_size; //Finally let us take care of endianess diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_hcode_image_build_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_hcode_image_build_errors.xml index 9d8fbb6ee..21823b931 100755 --- a/src/import/chips/p9/procedures/xml/error_info/p9_hcode_image_build_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_hcode_image_build_errors.xml @@ -375,6 +375,21 @@ </hwpError> <!-- *********************************************************************** --> <hwpError> + <rc>RC_P9_PGPE_AUX_TASK_BUILD_FAIL</rc> + <description>hcode image build procedure failed to update PGPE Aux Task region of HOMER. + Note: 0xFFFFFFFF in field MAX_ALLOWED_SIZE is an invalid size suggesting that image + section is not found</description> + <ffdc>EC_LEVEL</ffdc> + <ffdc>CHIP_TYPE</ffdc> + <ffdc>MAX_ALLOWED_SIZE</ffdc> + <ffdc>ACTUAL_SIZE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> <rc>RC_CORE_SCAN_RING_EXTRACTION_FAIL</rc> <description>hcode image build procedure failed to extract core scan rings</description> <ffdc>EXTRACTION_FAILURE_CODE</ffdc> |
