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authorRyan Black <rblack@us.ibm.com>2017-12-05 00:09:59 -0600
committerDaniel M. Crowell <dcrowell@us.ibm.com>2018-03-13 10:21:53 -0400
commit17165d955d01e44bb292db8e861306769e4cbe1a (patch)
tree5d1ea9d16ff6a3a3add264b0913551a34c24808f /src/import
parent4c248c90a3054951fa6c511b3b4774e3546f0986 (diff)
downloadtalos-hostboot-17165d955d01e44bb292db8e861306769e4cbe1a.tar.gz
talos-hostboot-17165d955d01e44bb292db8e861306769e4cbe1a.zip
p9.npu.scom.initfile -- fix cq_sm allocation issue at low water mark
Change-Id: I0a83730298db3cb3a8898f4165748a29516946e7 Original-Change-Id: Ibf7f3276279e99e82841d2a209230ce38081c419 CQ: HW426816 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50480 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55601 CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import')
-rw-r--r--src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml24
1 files changed, 24 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
index 2f0ad8b6c..d61a9dbf7 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
@@ -5747,6 +5747,30 @@
</chip>
</chipEcFeature>
</attribute>
+ <!-- ******************************************************************** -->
+ <attribute>
+ <id>ATTR_CHIP_EC_FEATURE_HW426816</id>>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+ Nimbus DD2.0-DD2.2/Cumulus DD1.0-DD1.1: CQ_SM allocation: Simultaneous free+allocate at the low water mark causes incorrect increment of reserved counter.
+ </description>
+ <chipEcFeature>
+ <chip>
+ <name>ENUM_ATTR_NAME_NIMBUS</name>
+ <ec>
+ <value>0x20</value>
+ <test>GREATER_THAN_OR_EQUAL</test>
+ </ec>
+ </chip>
+ <chip>
+ <name>ENUM_ATTR_NAME_CUMULUS</name>
+ <ec>
+ <value>0x10</value>
+ <test>GREATER_THAN_OR_EQUAL</test>
+ </ec>
+ </chip>
+ </chipEcFeature>
+ </attribute>
<!-- ******************************************************************** -->
<!-- NOTE: This attribute is used in an initfile to qualify the contents
of a GPTR ring. There is special processing in place to move the
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