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| author | Anusha Reddy Rangareddygari <anusrang@in.ibm.com> | 2016-06-27 15:16:54 +0200 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-06-28 12:43:17 -0400 |
| commit | 075f05fb73aa990f9f4040c5f3219df991fce228 (patch) | |
| tree | ae192fa3b09f59545cdb1034b9cd35ee13024037 /src/import | |
| parent | 2af3c06087ba4cac442fe3c771f949effee014c0 (diff) | |
| download | talos-hostboot-075f05fb73aa990f9f4040c5f3219df991fce228.tar.gz talos-hostboot-075f05fb73aa990f9f4040c5f3219df991fce228.zip | |
Level 2 HWP for p9_sbe_npll_setup
Change-Id: I33fda7070a01cafe01beac0b69c5ebaa77e0c6ed
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26288
Tested-by: Jenkins Server
Tested-by: PPE CI
Tested-by: Hostboot CI
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: Sunil Kumar <skumar8j@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26290
Tested-by: FSP CI Jenkins
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml | 31 | ||||
| -rw-r--r-- | src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml | 9 |
2 files changed, 37 insertions, 3 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml index db1b07130..f2e4c67dd 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml @@ -35,7 +35,7 @@ <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description>Clock Mux#0 settings</description> <valueType>uint8</valueType> - <writeable/> + <platInit/> </attribute> <attribute> @@ -349,8 +349,9 @@ <id>ATTR_ECID</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description>Bits 0 to 63 of the ECID in array entry 0 and bits 64 to 127 in ECID array entry 1 -Created from running the mss_get_cen_ecid.C -Firmware shares some code with the processor, so the attribute is named so they can point at a target and have common function.</description> + Created from running the mss_get_cen_ecid.C + Firmware shares some code with the processor, + so the attribute is named so they can point at a target and have common function.</description> <valueType>uint64</valueType> <writeable/> <odmVisable/> @@ -656,4 +657,28 @@ Firmware shares some code with the processor, so the attribute is named so they <platInit/> </attribute> +<attribute> + <id>ATTR_CP_FILTER_BYPASS</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>To skip the locking sequence and check for lock of CP PLL</description> + <valueType>uint8</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_SS_FILTER_BYPASS</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>To skip the locking sequence and check for lock of SS PLL</description> + <valueType>uint8</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_IO_FILTER_BYPASS</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>To skip the locking sequence and check for lock of IO PLL</description> + <valueType>uint8</valueType> + <platInit/> +</attribute> + </attributes> diff --git a/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml b/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml index 473e860c6..86526c25e 100644 --- a/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml +++ b/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml @@ -229,6 +229,15 @@ <attribute> <id>ATTR_MSS_VPD_MT_MC_DQ_CTLE_RES</id> </attribute> + <attribute> + <id>ATTR_SS_FILTER_BYPASS</id> + </attribute> + <attribute> + <id>ATTR_CP_FILTER_BYPASS</id> + </attribute> + <attribute> + <id>ATTR_IO_FILTER_BYPASS</id> + </attribute> <!-- ===================================================================== End of temporary definitions ================================================================= --> |
