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| author | Louis Stermole <stermole@us.ibm.com> | 2018-12-17 08:46:03 -0500 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2019-02-15 14:36:56 -0600 |
| commit | da8dc237c389736461f396c0b635ee2bbdca5755 (patch) | |
| tree | 0fe56a5dd7d213549a1b40cdfcf65ad0e326c143 /src/import/generic | |
| parent | 5cc4d102d8c829ea2b2b5bcd04e1cbcbacfa050c (diff) | |
| download | talos-hostboot-da8dc237c389736461f396c0b635ee2bbdca5755.tar.gz talos-hostboot-da8dc237c389736461f396c0b635ee2bbdca5755.zip | |
Add new MSS attributes for Axone
ATTR_MEM_MRW_IS_PLANAR
ATTR_MEM_EFF_DIMM_SPARE
ATTR_MEM_VPD_DQ_MAP
Change-Id: I1e63f4d6113f4adbcd7f149f00c14bb023115611
Original-Change-Id: I36915bf7aa8c6fffc3e8b27aea595d9feb1760dc
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69903
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71934
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/generic')
| -rw-r--r-- | src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml b/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml index 700cb20b9..c94dc98fe 100644 --- a/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml +++ b/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml @@ -647,6 +647,21 @@ </attribute> <attribute> + <id>ATTR_MEM_EFF_DIMM_SPARE</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Spare DRAM availability. Used in various locations and is computed in mss_eff_cnfg. + Array indexes are [DIMM][RANK] + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum>NO_SPARE = 0, LOW_NIBBLE = 1, HIGH_NIBBLE = 2, FULL_BYTE = 3</enum> + <writeable/> + <array> 2 4</array> + <mssAccessorName>dimm_spare</mssAccessorName> + </attribute> + + <attribute> <id>ATTR_MEM_EFF_DRAM_CL</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> |
