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author | Stephen Glancy <sglancy@us.ibm.com> | 2019-12-03 14:09:50 -0500 |
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committer | Daniel M Crowell <dcrowell@us.ibm.com> | 2019-12-11 14:33:51 -0600 |
commit | 5b24dd1c63f337b2f20c2af56e9b9f3562e8c12d (patch) | |
tree | 9eda0652bbf713c8e407f5c61a9e7237ad945d90 /src/import/generic | |
parent | d1b590057bc0a0effb94a589ac8ab590425fc28d (diff) | |
download | talos-hostboot-5b24dd1c63f337b2f20c2af56e9b9f3562e8c12d.tar.gz talos-hostboot-5b24dd1c63f337b2f20c2af56e9b9f3562e8c12d.zip |
Updates MCBIST print statements
Change-Id: Icb204ded9548ffe76fc01c55804f7f6a32cdd20c
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/87990
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/88163
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/generic')
-rw-r--r-- | src/import/generic/memory/lib/utils/mc/gen_mss_port.H | 109 |
1 files changed, 109 insertions, 0 deletions
diff --git a/src/import/generic/memory/lib/utils/mc/gen_mss_port.H b/src/import/generic/memory/lib/utils/mc/gen_mss_port.H index d8351be54..01c704e89 100644 --- a/src/import/generic/memory/lib/utils/mc/gen_mss_port.H +++ b/src/import/generic/memory/lib/utils/mc/gen_mss_port.H @@ -48,6 +48,115 @@ namespace mss { /// +/// @brief Reads the farb0q register +/// @tparam MC the memory controller type +/// @tparam T the fapi2 target type of the target +/// @tparam TT the class traits for the port +/// @param[in] i_target the target +/// @param[out] o_data data read from the register +/// @return FAPI2_RC_SUCCESS if and only if ok +/// @note Disable Port Fail after recurring RCD errors. +/// +template< mss::mc_type MC = DEFAULT_MC_TYPE, fapi2::TargetType T, typename TT = portTraits<MC> > +fapi2::ReturnCode read_farb0q( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) +{ + FAPI_TRY( mss::getScom(i_target, TT::FARB0Q_REG, o_data) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Writes the farb0q register +/// @tparam MC the memory controller type +/// @tparam T the fapi2 target type of the target +/// @tparam TT the class traits for the port +/// @param[in] i_target the target +/// @param[in] i_data data read from the register +/// @return FAPI2_RC_SUCCESS if and only if ok +/// @note Disable Port Fail after recurring RCD errors. +/// +template< mss::mc_type MC = DEFAULT_MC_TYPE, fapi2::TargetType T, typename TT = portTraits<MC> > +fapi2::ReturnCode write_farb0q( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) +{ + FAPI_TRY( mss::putScom(i_target, TT::FARB0Q_REG, i_data) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Reads the farb6q register +/// @tparam MC the memory controller type +/// @tparam T the fapi2 target type of the target +/// @tparam TT the class traits for the port +/// @param[in] i_target the target +/// @param[out] o_data data read from the register +/// @return FAPI2_RC_SUCCESS if and only if ok +/// @note Disable Port Fail after recurring RCD errors. +/// +template< mss::mc_type MC = DEFAULT_MC_TYPE, fapi2::TargetType T, typename TT = portTraits<MC> > +fapi2::ReturnCode read_farb6q( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) +{ + FAPI_TRY( mss::getScom(i_target, TT::FARB6Q_REG, o_data) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Writes the farb6q register +/// @tparam MC the memory controller type +/// @tparam T the fapi2 target type of the target +/// @tparam TT the class traits for the port +/// @param[in] i_target the target +/// @param[in] i_data data read from the register +/// @return FAPI2_RC_SUCCESS if and only if ok +/// @note Disable Port Fail after recurring RCD errors. +/// +template< mss::mc_type MC = DEFAULT_MC_TYPE, fapi2::TargetType T, typename TT = portTraits<MC> > +fapi2::ReturnCode write_farb6q( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) +{ + FAPI_TRY( mss::putScom(i_target, TT::FARB6Q_REG, i_data) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Gets the bandwidth window data +/// @tparam MC the memory controller type +/// @tparam TT the class traits for the port +/// @param[in] i_data data read from the register +/// @param[out] o_bw_window +/// @return FAPI2_RC_SUCCESS if and only if ok +/// @note Disable Port Fail after recurring RCD errors. +/// +template< mss::mc_type MC = DEFAULT_MC_TYPE, typename TT = portTraits<MC> > +void get_bw_window( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_bw_window ) +{ + o_bw_window = 0; + i_data.extractToRight<TT::BW_WINDOW_SIZE, TT::BW_WINDOW_SIZE_LEN>(o_bw_window); +} + +/// +/// @brief Gets the bandwidth snapshot +/// @tparam MC the memory controller type +/// @tparam TT the class traits for the port +/// @param[in] i_data data read from the register +/// @param[out] o_bw_snapshot +/// @return FAPI2_RC_SUCCESS if and only if ok +/// @note Disable Port Fail after recurring RCD errors. +/// +template< mss::mc_type MC = DEFAULT_MC_TYPE, typename TT = portTraits<MC> > +void get_bw_snapshot( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_bw_snapshot ) +{ + o_bw_snapshot = 0; + i_data.extractToRight<TT::BW_SNAPSHOT, TT::BW_SNAPSHOT_LEN>(o_bw_snapshot); +} + + +/// /// @brief ATTR_MSS_MVPD_FWMS getter declare /// @tparam MC the memory controller type /// @tparam T the fapi2 target type of the target |