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authorMark Pizzutillo <Mark.Pizzutillo@ibm.com>2019-04-15 16:04:36 -0400
committerChristian R. Geddes <crgeddes@us.ibm.com>2019-04-24 11:17:45 -0500
commit2007c4f940856589a087452beac9a20359098b0b (patch)
tree959a6e2654858c4282f6e5001c2d8425d236eb44 /src/import/generic/memory/lib/spd
parentf43f8bd48e3f930d78a95566c720d272f0779d94 (diff)
downloadtalos-hostboot-2007c4f940856589a087452beac9a20359098b0b.tar.gz
talos-hostboot-2007c4f940856589a087452beac9a20359098b0b.zip
Add SPD getters for PMIC fields
Change-Id: I8ca5ee5937cf02e4e503e9eac9665ef17882ad36 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75996 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76182 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/generic/memory/lib/spd')
-rw-r--r--src/import/generic/memory/lib/spd/common/dimm_module_decoder.H150
-rw-r--r--src/import/generic/memory/lib/spd/ddimm/ddr4/ddimm_decoder_ddr4.H202
-rw-r--r--src/import/generic/memory/lib/spd/spd_facade.H154
-rw-r--r--src/import/generic/memory/lib/spd/spd_fields_ddr4.H138
-rw-r--r--src/import/generic/memory/lib/spd/spd_traits_ddr4.H237
5 files changed, 678 insertions, 203 deletions
diff --git a/src/import/generic/memory/lib/spd/common/dimm_module_decoder.H b/src/import/generic/memory/lib/spd/common/dimm_module_decoder.H
index 11e5f3a6e..8ff2e30fa 100644
--- a/src/import/generic/memory/lib/spd/common/dimm_module_decoder.H
+++ b/src/import/generic/memory/lib/spd/common/dimm_module_decoder.H
@@ -953,7 +953,7 @@ class dimm_module_decoder
}
///
- /// @brief Decodes PMIC0 SWA Voltage Setting -> PMIC0_SWA_RANGE
+ /// @brief Decodes PMIC0 SWA Voltage Setting -> PMIC0_SWA_RANGE_SETTING
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
@@ -975,11 +975,22 @@ class dimm_module_decoder
}
///
- /// @brief Decodes PMIC0 SWA Voltage Offset -> PMIC0_SWA_OFF_RANGE
+ /// @brief Decodes PMIC0 SWA Voltage Offset -> PMIC0_SWA_OFF_DIRECTION
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
- virtual fapi2::ReturnCode volt_offset_range_swa_pmic0(uint8_t& o_output) const
+ virtual fapi2::ReturnCode volt_offset_direction_swa_pmic0(uint8_t& o_output) const
+ {
+ o_output = 0;
+ return fapi2::FAPI2_RC_SUCCESS;
+ }
+
+ ///
+ /// @brief Decodes PMIC0 SWA Delay -> PMIC0_SWA_DELAY
+ /// @param[out] o_output encoding from SPD
+ /// @return FAPI2_RC_SUCCESS if okay
+ ///
+ virtual fapi2::ReturnCode volt_delay_swa_pmic0(uint8_t& o_output) const
{
o_output = 0;
return fapi2::FAPI2_RC_SUCCESS;
@@ -1008,7 +1019,7 @@ class dimm_module_decoder
}
///
- /// @brief Decodes PMIC0 SWB Voltage Setting -> PMIC0_SWB_RANGE
+ /// @brief Decodes PMIC0 SWB Voltage Setting -> PMIC0_SWB_RANGE_SETTING
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
@@ -1030,18 +1041,29 @@ class dimm_module_decoder
}
///
- /// @brief Decodes PMIC0 SWB Voltage Offset -> PMIC0_SWB_OFF_RANGE
+ /// @brief Decodes PMIC0 SWB Voltage Offset -> PMIC0_SWB_OFF_DIRECTION
+ /// @param[out] o_output encoding from SPD
+ /// @return FAPI2_RC_SUCCESS if okay
+ ///
+ virtual fapi2::ReturnCode volt_offset_direction_swb_pmic0(uint8_t& o_output) const
+ {
+ o_output = 0;
+ return fapi2::FAPI2_RC_SUCCESS;
+ }
+
+ ///
+ /// @brief Decodes PMIC0 SWB Delay -> PMIC0_SWB_DELAY
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
- virtual fapi2::ReturnCode volt_offset_range_swb_pmic0(uint8_t& o_output) const
+ virtual fapi2::ReturnCode volt_delay_swb_pmic0(uint8_t& o_output) const
{
o_output = 0;
return fapi2::FAPI2_RC_SUCCESS;
}
///
- /// @brief Decodes PMIC0 SWB Delay Sequence Order -> PMIC0_SWB_ORDER
+ /// @brief Decodes PMIC0 SWB Sequence Order -> PMIC0_SWB_ORDER
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
@@ -1063,7 +1085,7 @@ class dimm_module_decoder
}
///
- /// @brief Decodes PMIC0 SWC Voltage Setting -> PMIC0_SWC_RANGE
+ /// @brief Decodes PMIC0 SWC Voltage Setting -> PMIC0_SWC_RANGE_SETTING
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
@@ -1085,18 +1107,29 @@ class dimm_module_decoder
}
///
- /// @brief Decodes PMIC0 SWC Voltage Offset -> PMIC0_SWC_OFF_RANGE
+ /// @brief Decodes PMIC0 SWC Voltage Offset -> PMIC0_SWC_OFF_DIRECTION
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
- virtual fapi2::ReturnCode volt_offset_range_swc_pmic0(uint8_t& o_output) const
+ virtual fapi2::ReturnCode volt_offset_direction_swc_pmic0(uint8_t& o_output) const
{
o_output = 0;
return fapi2::FAPI2_RC_SUCCESS;
}
///
- /// @brief Decodes PMIC0 SWC Delay Sequence Order -> PMIC0_SWC_ORDER
+ /// @brief Decodes PMIC0 SWC Delay -> PMIC0_SWC_DELAY
+ /// @param[out] o_output encoding from SPD
+ /// @return FAPI2_RC_SUCCESS if okay
+ ///
+ virtual fapi2::ReturnCode volt_delay_swc_pmic0(uint8_t& o_output) const
+ {
+ o_output = 0;
+ return fapi2::FAPI2_RC_SUCCESS;
+ }
+
+ ///
+ /// @brief Decodes PMIC0 SWC Sequence Order -> PMIC0_SWC_ORDER
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
@@ -1118,7 +1151,7 @@ class dimm_module_decoder
}
///
- /// @brief Decodes PMIC0 SWD Voltage Setting -> PMIC0_SWD_RANGE
+ /// @brief Decodes PMIC0 SWD Voltage Setting -> PMIC0_SWD_RANGE_SETTING
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
@@ -1140,18 +1173,29 @@ class dimm_module_decoder
}
///
- /// @brief Decodes PMIC0 SWD Voltage Offset -> PMIC0_SWD_OFF_RANGE
+ /// @brief Decodes PMIC0 SWD Voltage Offset -> PMIC0_SWD_OFF_DIRECTION
+ /// @param[out] o_output encoding from SPD
+ /// @return FAPI2_RC_SUCCESS if okay
+ ///
+ virtual fapi2::ReturnCode volt_offset_direction_swd_pmic0(uint8_t& o_output) const
+ {
+ o_output = 0;
+ return fapi2::FAPI2_RC_SUCCESS;
+ }
+
+ ///
+ /// @brief Decodes PMIC0 SWD Delay -> PMIC0_SWD_DELAY
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
- virtual fapi2::ReturnCode volt_offset_range_swd_pmic0(uint8_t& o_output) const
+ virtual fapi2::ReturnCode volt_delay_swd_pmic0(uint8_t& o_output) const
{
o_output = 0;
return fapi2::FAPI2_RC_SUCCESS;
}
///
- /// @brief Decodes PMIC0 SWD Delay Sequence Order -> PMIC0_SWD_ORDER
+ /// @brief Decodes PMIC0 SWD Sequence Order -> PMIC0_SWD_ORDER
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
@@ -1184,7 +1228,7 @@ class dimm_module_decoder
}
///
- /// @brief Decodes PMIC1 SWA Voltage Setting -> PMIC1_SWA_RANGE
+ /// @brief Decodes PMIC1 SWA Voltage Setting -> PMIC1_SWA_RANGE_SETTING
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
@@ -1206,18 +1250,29 @@ class dimm_module_decoder
}
///
- /// @brief Decodes PMIC1 SWA Voltage Offset -> PMIC1_SWA_OFF_RANGE
+ /// @brief Decodes PMIC1 SWA Voltage Offset -> PMIC1_SWA_OFF_DIRECTION
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
- virtual fapi2::ReturnCode volt_offset_range_swa_pmic1(uint8_t& o_output) const
+ virtual fapi2::ReturnCode volt_offset_direction_swa_pmic1(uint8_t& o_output) const
{
o_output = 0;
return fapi2::FAPI2_RC_SUCCESS;
}
///
- /// @brief Decodes PMIC1 SWA Delay Sequence Order -> PMIC1_SWA_ORDER
+ /// @brief Decodes PMIC1 SWA Delay -> PMIC1_SWA_DELAY
+ /// @param[out] o_output encoding from SPD
+ /// @return FAPI2_RC_SUCCESS if okay
+ ///
+ virtual fapi2::ReturnCode volt_delay_swa_pmic1(uint8_t& o_output) const
+ {
+ o_output = 0;
+ return fapi2::FAPI2_RC_SUCCESS;
+ }
+
+ ///
+ /// @brief Decodes PMIC1 SWA Sequence Order -> PMIC1_SWA_ORDER
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
@@ -1239,7 +1294,7 @@ class dimm_module_decoder
}
///
- /// @brief Decodes PMIC1 SWB Voltage Setting -> PMIC1_SWB_RANGE
+ /// @brief Decodes PMIC1 SWB Voltage Setting -> PMIC1_SWB_RANGE_SETTING
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
@@ -1261,18 +1316,29 @@ class dimm_module_decoder
}
///
- /// @brief Decodes PMIC1 SWB Voltage Offset -> PMIC1_SWB_OFF_RANGE
+ /// @brief Decodes PMIC1 SWB Voltage Offset -> PMIC1_SWB_OFF_DIRECTION
+ /// @param[out] o_output encoding from SPD
+ /// @return FAPI2_RC_SUCCESS if okay
+ ///
+ virtual fapi2::ReturnCode volt_offset_direction_swb_pmic1(uint8_t& o_output) const
+ {
+ o_output = 0;
+ return fapi2::FAPI2_RC_SUCCESS;
+ }
+
+ ///
+ /// @brief Decodes PMIC1 SWB Delay -> PMIC1_SWB_DELAY
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
- virtual fapi2::ReturnCode volt_offset_range_swb_pmic1(uint8_t& o_output) const
+ virtual fapi2::ReturnCode volt_delay_swb_pmic1(uint8_t& o_output) const
{
o_output = 0;
return fapi2::FAPI2_RC_SUCCESS;
}
///
- /// @brief Decodes PMIC1 SWB Delay Sequence Order -> PMIC1_SWB_ORDER
+ /// @brief Decodes PMIC1 SWB Sequence Order -> PMIC1_SWB_ORDER
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
@@ -1294,7 +1360,7 @@ class dimm_module_decoder
}
///
- /// @brief Decodes PMIC1 SWC Voltage Setting -> PMIC1_SWC_RANGE
+ /// @brief Decodes PMIC1 SWC Voltage Setting -> PMIC1_SWC_RANGE_SETTING
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
@@ -1316,18 +1382,29 @@ class dimm_module_decoder
}
///
- /// @brief Decodes PMIC1 SWC Voltage Offset -> PMIC1_SWC_OFF_RANGE
+ /// @brief Decodes PMIC1 SWC Voltage Offset -> PMIC1_SWC_OFF_DIRECTION
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
- virtual fapi2::ReturnCode volt_offset_range_swc_pmic1(uint8_t& o_output) const
+ virtual fapi2::ReturnCode volt_offset_direction_swc_pmic1(uint8_t& o_output) const
{
o_output = 0;
return fapi2::FAPI2_RC_SUCCESS;
}
///
- /// @brief Decodes PMIC1 SWC Delay Sequence Order -> PMIC1_SWC_ORDER
+ /// @brief Decodes PMIC1 SWC Delay -> PMIC1_SWC_DELAY
+ /// @param[out] o_output encoding from SPD
+ /// @return FAPI2_RC_SUCCESS if okay
+ ///
+ virtual fapi2::ReturnCode volt_delay_swc_pmic1(uint8_t& o_output) const
+ {
+ o_output = 0;
+ return fapi2::FAPI2_RC_SUCCESS;
+ }
+
+ ///
+ /// @brief Decodes PMIC1 SWC Sequence Order -> PMIC1_SWC_ORDER
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
@@ -1349,7 +1426,7 @@ class dimm_module_decoder
}
///
- /// @brief Decodes PMIC1 SWD Voltage Setting -> PMIC1_SWD_RANGE
+ /// @brief Decodes PMIC1 SWD Voltage Setting -> PMIC1_SWD_RANGE_SETTING
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
@@ -1371,18 +1448,29 @@ class dimm_module_decoder
}
///
- /// @brief Decodes PMIC1 SWD Voltage Offset -> PMIC1_SWD_OFF_RANGE
+ /// @brief Decodes PMIC1 SWD Voltage Offset -> PMIC1_SWD_OFF_DIRECTION
+ /// @param[out] o_output encoding from SPD
+ /// @return FAPI2_RC_SUCCESS if okay
+ ///
+ virtual fapi2::ReturnCode volt_offset_direction_swd_pmic1(uint8_t& o_output) const
+ {
+ o_output = 0;
+ return fapi2::FAPI2_RC_SUCCESS;
+ }
+
+ ///
+ /// @brief Decodes PMIC1 SWD Delay -> PMIC1_SWD_DELAY
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
- virtual fapi2::ReturnCode volt_offset_range_swd_pmic1(uint8_t& o_output) const
+ virtual fapi2::ReturnCode volt_delay_swd_pmic1(uint8_t& o_output) const
{
o_output = 0;
return fapi2::FAPI2_RC_SUCCESS;
}
///
- /// @brief Decodes PMIC1 SWD Delay Sequence Order -> PMIC1_SWD_ORDER
+ /// @brief Decodes PMIC1 SWD Sequence Order -> PMIC1_SWD_ORDER
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
diff --git a/src/import/generic/memory/lib/spd/ddimm/ddr4/ddimm_decoder_ddr4.H b/src/import/generic/memory/lib/spd/ddimm/ddr4/ddimm_decoder_ddr4.H
index 2d1816ab3..00f893a39 100644
--- a/src/import/generic/memory/lib/spd/ddimm/ddr4/ddimm_decoder_ddr4.H
+++ b/src/import/generic/memory/lib/spd/ddimm/ddr4/ddimm_decoder_ddr4.H
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2018 */
+/* Contributors Listed Below - COPYRIGHT 2018,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -763,13 +763,13 @@ class decoder<DDR4, DDIMM_MODULE, R > : public dimm_module_decoder
}
///
- /// @brief Decodes PMIC0 SWA Voltage Setting -> PMIC0_SWA_RANGE
+ /// @brief Decodes PMIC0 SWA Voltage Setting -> PMIC0_SWA_RANGE_SELECT
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
virtual fapi2::ReturnCode volt_setpoint_range_swa_pmic0(uint8_t& o_output) const override
{
- FAPI_TRY( (mss::spd::reader<fields_t::PMIC0_SWA_RANGE, R>(iv_target, iv_data, o_output)) );
+ FAPI_TRY( (mss::spd::reader<fields_t::PMIC0_SWA_RANGE_SELECT, R>(iv_target, iv_data, o_output)) );
fapi_try_exit:
return fapi2::current_err;
@@ -789,20 +789,33 @@ class decoder<DDR4, DDIMM_MODULE, R > : public dimm_module_decoder
}
///
- /// @brief Decodes PMIC0 SWA Voltage Offset -> PMIC0_SWA_OFF_RANGE
+ /// @brief Decodes PMIC0 SWA Voltage Offset -> PMIC0_SWA_OFF_DIRECTION
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
- virtual fapi2::ReturnCode volt_offset_range_swa_pmic0(uint8_t& o_output) const override
+ virtual fapi2::ReturnCode volt_offset_direction_swa_pmic0(uint8_t& o_output) const override
{
- FAPI_TRY( (mss::spd::reader<fields_t::PMIC0_SWA_OFF_RANGE, R>(iv_target, iv_data, o_output)) );
+ FAPI_TRY( (mss::spd::reader<fields_t::PMIC0_SWA_OFF_DIRECTION, R>(iv_target, iv_data, o_output)) );
fapi_try_exit:
return fapi2::current_err;
}
///
- /// @brief Decodes PMIC0 SWA Delay Sequence Order -> PMIC0_SWA_ORDER
+ /// @brief Decodes PMIC0 SWA Sequence Delay -> PMIC0_SWA_DELAY
+ /// @param[out] o_output encoding from SPD
+ /// @return FAPI2_RC_SUCCESS if okay
+ ///
+ virtual fapi2::ReturnCode volt_delay_swa_pmic0(uint8_t& o_output) const override
+ {
+ FAPI_TRY( (mss::spd::reader<fields_t::PMIC0_SWA_DELAY, R>(iv_target, iv_data, o_output)) );
+
+ fapi_try_exit:
+ return fapi2::current_err;
+ }
+
+ ///
+ /// @brief Decodes PMIC0 SWA Sequence Order -> PMIC0_SWA_ORDER
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
@@ -828,13 +841,13 @@ class decoder<DDR4, DDIMM_MODULE, R > : public dimm_module_decoder
}
///
- /// @brief Decodes PMIC0 SWB Voltage Setting -> PMIC0_SWB_RANGE
+ /// @brief Decodes PMIC0 SWB Voltage Setting -> PMIC0_SWB_RANGE_SELECT
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
virtual fapi2::ReturnCode volt_setpoint_range_swb_pmic0(uint8_t& o_output) const override
{
- FAPI_TRY( (mss::spd::reader<fields_t::PMIC0_SWB_RANGE, R>(iv_target, iv_data, o_output)) );
+ FAPI_TRY( (mss::spd::reader<fields_t::PMIC0_SWB_RANGE_SELECT, R>(iv_target, iv_data, o_output)) );
fapi_try_exit:
return fapi2::current_err;
@@ -854,20 +867,33 @@ class decoder<DDR4, DDIMM_MODULE, R > : public dimm_module_decoder
}
///
- /// @brief Decodes PMIC0 SWB Voltage Offset -> PMIC0_SWB_OFF_RANGE
+ /// @brief Decodes PMIC0 SWB Voltage Offset -> PMIC0_SWB_OFF_DIRECTION
+ /// @param[out] o_output encoding from SPD
+ /// @return FAPI2_RC_SUCCESS if okay
+ ///
+ virtual fapi2::ReturnCode volt_offset_direction_swb_pmic0(uint8_t& o_output) const override
+ {
+ FAPI_TRY( (mss::spd::reader<fields_t::PMIC0_SWB_OFF_DIRECTION, R>(iv_target, iv_data, o_output)) );
+
+ fapi_try_exit:
+ return fapi2::current_err;
+ }
+
+ ///
+ /// @brief Decodes PMIC0 SWB Sequence Delay -> PMIC0_SWB_DELAY
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
- virtual fapi2::ReturnCode volt_offset_range_swb_pmic0(uint8_t& o_output) const override
+ virtual fapi2::ReturnCode volt_delay_swb_pmic0(uint8_t& o_output) const override
{
- FAPI_TRY( (mss::spd::reader<fields_t::PMIC0_SWB_OFF_RANGE, R>(iv_target, iv_data, o_output)) );
+ FAPI_TRY( (mss::spd::reader<fields_t::PMIC0_SWB_DELAY, R>(iv_target, iv_data, o_output)) );
fapi_try_exit:
return fapi2::current_err;
}
///
- /// @brief Decodes PMIC0 SWB Delay Sequence Order -> PMIC0_SWB_ORDER
+ /// @brief Decodes PMIC0 SWB Sequence Order -> PMIC0_SWB_ORDER
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
@@ -893,13 +919,13 @@ class decoder<DDR4, DDIMM_MODULE, R > : public dimm_module_decoder
}
///
- /// @brief Decodes PMIC0 SWC Voltage Setting -> PMIC0_SWC_RANGE
+ /// @brief Decodes PMIC0 SWC Voltage Setting -> PMIC0_SWC_RANGE_SELECT
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
virtual fapi2::ReturnCode volt_setpoint_range_swc_pmic0(uint8_t& o_output) const override
{
- FAPI_TRY( (mss::spd::reader<fields_t::PMIC0_SWC_RANGE, R>(iv_target, iv_data, o_output)) );
+ FAPI_TRY( (mss::spd::reader<fields_t::PMIC0_SWC_RANGE_SELECT, R>(iv_target, iv_data, o_output)) );
fapi_try_exit:
return fapi2::current_err;
@@ -919,20 +945,33 @@ class decoder<DDR4, DDIMM_MODULE, R > : public dimm_module_decoder
}
///
- /// @brief Decodes PMIC0 SWC Voltage Offset -> PMIC0_SWC_OFF_RANGE
+ /// @brief Decodes PMIC0 SWC Voltage Offset -> PMIC0_SWC_OFF_DIRECTION
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
- virtual fapi2::ReturnCode volt_offset_range_swc_pmic0(uint8_t& o_output) const override
+ virtual fapi2::ReturnCode volt_offset_direction_swc_pmic0(uint8_t& o_output) const override
{
- FAPI_TRY( (mss::spd::reader<fields_t::PMIC0_SWC_OFF_RANGE, R>(iv_target, iv_data, o_output)) );
+ FAPI_TRY( (mss::spd::reader<fields_t::PMIC0_SWC_OFF_DIRECTION, R>(iv_target, iv_data, o_output)) );
fapi_try_exit:
return fapi2::current_err;
}
///
- /// @brief Decodes PMIC0 SWC Delay Sequence Order -> PMIC0_SWC_ORDER
+ /// @brief Decodes PMIC0 SWC Sequence Delay -> PMIC0_SWC_DELAY
+ /// @param[out] o_output encoding from SPD
+ /// @return FAPI2_RC_SUCCESS if okay
+ ///
+ virtual fapi2::ReturnCode volt_delay_swc_pmic0(uint8_t& o_output) const override
+ {
+ FAPI_TRY( (mss::spd::reader<fields_t::PMIC0_SWC_DELAY, R>(iv_target, iv_data, o_output)) );
+
+ fapi_try_exit:
+ return fapi2::current_err;
+ }
+
+ ///
+ /// @brief Decodes PMIC0 SWC Sequence Order -> PMIC0_SWC_ORDER
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
@@ -958,13 +997,13 @@ class decoder<DDR4, DDIMM_MODULE, R > : public dimm_module_decoder
}
///
- /// @brief Decodes PMIC0 SWD Voltage Setting -> PMIC0_SWD_RANGE
+ /// @brief Decodes PMIC0 SWD Voltage Setting -> PMIC0_SWD_RANGE_SELECT
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
virtual fapi2::ReturnCode volt_setpoint_range_swd_pmic0(uint8_t& o_output) const override
{
- FAPI_TRY( (mss::spd::reader<fields_t::PMIC0_SWD_RANGE, R>(iv_target, iv_data, o_output)) );
+ FAPI_TRY( (mss::spd::reader<fields_t::PMIC0_SWD_RANGE_SELECT, R>(iv_target, iv_data, o_output)) );
fapi_try_exit:
return fapi2::current_err;
@@ -984,20 +1023,33 @@ class decoder<DDR4, DDIMM_MODULE, R > : public dimm_module_decoder
}
///
- /// @brief Decodes PMIC0 SWD Voltage Offset -> PMIC0_SWD_OFF_RANGE
+ /// @brief Decodes PMIC0 SWD Voltage Offset -> PMIC0_SWD_OFF_DIRECTION
+ /// @param[out] o_output encoding from SPD
+ /// @return FAPI2_RC_SUCCESS if okay
+ ///
+ virtual fapi2::ReturnCode volt_offset_direction_swd_pmic0(uint8_t& o_output) const override
+ {
+ FAPI_TRY( (mss::spd::reader<fields_t::PMIC0_SWD_OFF_DIRECTION, R>(iv_target, iv_data, o_output)) );
+
+ fapi_try_exit:
+ return fapi2::current_err;
+ }
+
+ ///
+ /// @brief Decodes PMIC0 SWD Sequence Delay -> PMIC0_SWD_DELAY
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
- virtual fapi2::ReturnCode volt_offset_range_swd_pmic0(uint8_t& o_output) const override
+ virtual fapi2::ReturnCode volt_delay_swd_pmic0(uint8_t& o_output) const override
{
- FAPI_TRY( (mss::spd::reader<fields_t::PMIC0_SWD_OFF_RANGE, R>(iv_target, iv_data, o_output)) );
+ FAPI_TRY( (mss::spd::reader<fields_t::PMIC0_SWD_DELAY, R>(iv_target, iv_data, o_output)) );
fapi_try_exit:
return fapi2::current_err;
}
///
- /// @brief Decodes PMIC0 SWD Delay Sequence Order -> PMIC0_SWD_ORDER
+ /// @brief Decodes PMIC0 SWD Sequence Order -> PMIC0_SWD_ORDER
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
@@ -1036,13 +1088,13 @@ class decoder<DDR4, DDIMM_MODULE, R > : public dimm_module_decoder
}
///
- /// @brief Decodes PMIC1 SWA Voltage Setting -> PMIC1_SWA_RANGE
+ /// @brief Decodes PMIC1 SWA Voltage Setting -> PMIC1_SWA_RANGE_SELECT
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
virtual fapi2::ReturnCode volt_setpoint_range_swa_pmic1(uint8_t& o_output) const override
{
- FAPI_TRY( (mss::spd::reader<fields_t::PMIC1_SWA_RANGE, R>(iv_target, iv_data, o_output)) );
+ FAPI_TRY( (mss::spd::reader<fields_t::PMIC1_SWA_RANGE_SELECT, R>(iv_target, iv_data, o_output)) );
fapi_try_exit:
return fapi2::current_err;
@@ -1062,20 +1114,33 @@ class decoder<DDR4, DDIMM_MODULE, R > : public dimm_module_decoder
}
///
- /// @brief Decodes PMIC1 SWA Voltage Offset -> PMIC1_SWA_OFF_RANGE
+ /// @brief Decodes PMIC1 SWA Voltage Offset -> PMIC1_SWA_OFF_DIRECTION
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
- virtual fapi2::ReturnCode volt_offset_range_swa_pmic1(uint8_t& o_output) const override
+ virtual fapi2::ReturnCode volt_offset_direction_swa_pmic1(uint8_t& o_output) const override
{
- FAPI_TRY( (mss::spd::reader<fields_t::PMIC1_SWA_OFF_RANGE, R>(iv_target, iv_data, o_output)) );
+ FAPI_TRY( (mss::spd::reader<fields_t::PMIC1_SWA_OFF_DIRECTION, R>(iv_target, iv_data, o_output)) );
fapi_try_exit:
return fapi2::current_err;
}
///
- /// @brief Decodes PMIC1 SWA Delay Sequence Order -> PMIC1_SWA_ORDER
+ /// @brief Decodes PMIC1 SWA Sequence Delay -> PMIC1_SWA_DELAY
+ /// @param[out] o_output encoding from SPD
+ /// @return FAPI2_RC_SUCCESS if okay
+ ///
+ virtual fapi2::ReturnCode volt_delay_swa_pmic1(uint8_t& o_output) const override
+ {
+ FAPI_TRY( (mss::spd::reader<fields_t::PMIC1_SWA_DELAY, R>(iv_target, iv_data, o_output)) );
+
+ fapi_try_exit:
+ return fapi2::current_err;
+ }
+
+ ///
+ /// @brief Decodes PMIC1 SWA Sequence Order -> PMIC1_SWA_ORDER
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
@@ -1101,13 +1166,13 @@ class decoder<DDR4, DDIMM_MODULE, R > : public dimm_module_decoder
}
///
- /// @brief Decodes PMIC1 SWB Voltage Setting -> PMIC1_SWB_RANGE
+ /// @brief Decodes PMIC1 SWB Voltage Setting -> PMIC1_SWB_RANGE_SELECT
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
virtual fapi2::ReturnCode volt_setpoint_range_swb_pmic1(uint8_t& o_output) const override
{
- FAPI_TRY( (mss::spd::reader<fields_t::PMIC1_SWB_RANGE, R>(iv_target, iv_data, o_output)) );
+ FAPI_TRY( (mss::spd::reader<fields_t::PMIC1_SWB_RANGE_SELECT, R>(iv_target, iv_data, o_output)) );
fapi_try_exit:
return fapi2::current_err;
@@ -1127,20 +1192,33 @@ class decoder<DDR4, DDIMM_MODULE, R > : public dimm_module_decoder
}
///
- /// @brief Decodes PMIC1 SWB Voltage Offset -> PMIC1_SWB_OFF_RANGE
+ /// @brief Decodes PMIC1 SWB Voltage Offset -> PMIC1_SWB_OFF_DIRECTION
+ /// @param[out] o_output encoding from SPD
+ /// @return FAPI2_RC_SUCCESS if okay
+ ///
+ virtual fapi2::ReturnCode volt_offset_direction_swb_pmic1(uint8_t& o_output) const override
+ {
+ FAPI_TRY( (mss::spd::reader<fields_t::PMIC1_SWB_OFF_DIRECTION, R>(iv_target, iv_data, o_output)) );
+
+ fapi_try_exit:
+ return fapi2::current_err;
+ }
+
+ ///
+ /// @brief Decodes PMIC1 SWB Sequence Delay -> PMIC1_SWB_DELAY
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
- virtual fapi2::ReturnCode volt_offset_range_swb_pmic1(uint8_t& o_output) const override
+ virtual fapi2::ReturnCode volt_delay_swb_pmic1(uint8_t& o_output) const override
{
- FAPI_TRY( (mss::spd::reader<fields_t::PMIC1_SWB_OFF_RANGE, R>(iv_target, iv_data, o_output)) );
+ FAPI_TRY( (mss::spd::reader<fields_t::PMIC1_SWB_DELAY, R>(iv_target, iv_data, o_output)) );
fapi_try_exit:
return fapi2::current_err;
}
///
- /// @brief Decodes PMIC1 SWB Delay Sequence Order -> PMIC1_SWB_ORDER
+ /// @brief Decodes PMIC1 SWB Sequence Order -> PMIC1_SWB_ORDER
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
@@ -1166,13 +1244,13 @@ class decoder<DDR4, DDIMM_MODULE, R > : public dimm_module_decoder
}
///
- /// @brief Decodes PMIC1 SWC Voltage Setting -> PMIC1_SWC_RANGE
+ /// @brief Decodes PMIC1 SWC Voltage Setting -> PMIC1_SWC_RANGE_SELECT
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
virtual fapi2::ReturnCode volt_setpoint_range_swc_pmic1(uint8_t& o_output) const override
{
- FAPI_TRY( (mss::spd::reader<fields_t::PMIC1_SWC_RANGE, R>(iv_target, iv_data, o_output)) );
+ FAPI_TRY( (mss::spd::reader<fields_t::PMIC1_SWC_RANGE_SELECT, R>(iv_target, iv_data, o_output)) );
fapi_try_exit:
return fapi2::current_err;
@@ -1192,20 +1270,33 @@ class decoder<DDR4, DDIMM_MODULE, R > : public dimm_module_decoder
}
///
- /// @brief Decodes PMIC1 SWC Voltage Offset -> PMIC1_SWC_OFF_RANGE
+ /// @brief Decodes PMIC1 SWC Voltage Offset -> PMIC1_SWC_OFF_DIRECTION
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
- virtual fapi2::ReturnCode volt_offset_range_swc_pmic1(uint8_t& o_output) const override
+ virtual fapi2::ReturnCode volt_offset_direction_swc_pmic1(uint8_t& o_output) const override
{
- FAPI_TRY( (mss::spd::reader<fields_t::PMIC1_SWC_OFF_RANGE, R>(iv_target, iv_data, o_output)) );
+ FAPI_TRY( (mss::spd::reader<fields_t::PMIC1_SWC_OFF_DIRECTION, R>(iv_target, iv_data, o_output)) );
fapi_try_exit:
return fapi2::current_err;
}
///
- /// @brief Decodes PMIC1 SWC Delay Sequence Order -> PMIC1_SWC_ORDER
+ /// @brief Decodes PMIC1 SWC Sequence Delay -> PMIC1_SWC_DELAY
+ /// @param[out] o_output encoding from SPD
+ /// @return FAPI2_RC_SUCCESS if okay
+ ///
+ virtual fapi2::ReturnCode volt_delay_swc_pmic1(uint8_t& o_output) const override
+ {
+ FAPI_TRY( (mss::spd::reader<fields_t::PMIC1_SWC_DELAY, R>(iv_target, iv_data, o_output)) );
+
+ fapi_try_exit:
+ return fapi2::current_err;
+ }
+
+ ///
+ /// @brief Decodes PMIC1 SWC Sequence Order -> PMIC1_SWC_ORDER
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
@@ -1231,13 +1322,13 @@ class decoder<DDR4, DDIMM_MODULE, R > : public dimm_module_decoder
}
///
- /// @brief Decodes PMIC1 SWD Voltage Setting -> PMIC1_SWD_RANGE
+ /// @brief Decodes PMIC1 SWD Voltage Setting -> PMIC1_SWD_RANGE_SELECT
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
virtual fapi2::ReturnCode volt_setpoint_range_swd_pmic1(uint8_t& o_output) const override
{
- FAPI_TRY( (mss::spd::reader<fields_t::PMIC1_SWD_RANGE, R>(iv_target, iv_data, o_output)) );
+ FAPI_TRY( (mss::spd::reader<fields_t::PMIC1_SWD_RANGE_SELECT, R>(iv_target, iv_data, o_output)) );
fapi_try_exit:
return fapi2::current_err;
@@ -1257,20 +1348,33 @@ class decoder<DDR4, DDIMM_MODULE, R > : public dimm_module_decoder
}
///
- /// @brief Decodes PMIC1 SWD Voltage Offset -> PMIC1_SWD_OFF_RANGE
+ /// @brief Decodes PMIC1 SWD Voltage Offset -> PMIC1_SWD_OFF_DIRECTION
+ /// @param[out] o_output encoding from SPD
+ /// @return FAPI2_RC_SUCCESS if okay
+ ///
+ virtual fapi2::ReturnCode volt_offset_direction_swd_pmic1(uint8_t& o_output) const override
+ {
+ FAPI_TRY( (mss::spd::reader<fields_t::PMIC1_SWD_OFF_DIRECTION, R>(iv_target, iv_data, o_output)) );
+
+ fapi_try_exit:
+ return fapi2::current_err;
+ }
+
+ ///
+ /// @brief Decodes PMIC1 SWD Sequence Delay -> PMIC1_SWD_DELAY
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
- virtual fapi2::ReturnCode volt_offset_range_swd_pmic1(uint8_t& o_output) const override
+ virtual fapi2::ReturnCode volt_delay_swd_pmic1(uint8_t& o_output) const override
{
- FAPI_TRY( (mss::spd::reader<fields_t::PMIC1_SWD_OFF_RANGE, R>(iv_target, iv_data, o_output)) );
+ FAPI_TRY( (mss::spd::reader<fields_t::PMIC1_SWD_DELAY, R>(iv_target, iv_data, o_output)) );
fapi_try_exit:
return fapi2::current_err;
}
///
- /// @brief Decodes PMIC1 SWD Delay Sequence Order -> PMIC1_SWD_ORDER
+ /// @brief Decodes PMIC1 SWD Sequence Order -> PMIC1_SWD_ORDER
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
diff --git a/src/import/generic/memory/lib/spd/spd_facade.H b/src/import/generic/memory/lib/spd/spd_facade.H
index ed2fd357f..7f1769f77 100644
--- a/src/import/generic/memory/lib/spd/spd_facade.H
+++ b/src/import/generic/memory/lib/spd/spd_facade.H
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2018 */
+/* Contributors Listed Below - COPYRIGHT 2018,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -2035,16 +2035,29 @@ class facade final
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
- fapi2::ReturnCode volt_offset_range_swa_pmic0(uint8_t& o_output) const
+ fapi2::ReturnCode volt_offset_direction_swa_pmic0(uint8_t& o_output) const
{
- FAPI_TRY( iv_dimm_module_decoder->volt_offset_range_swa_pmic0(o_output) );
+ FAPI_TRY( iv_dimm_module_decoder->volt_offset_direction_swa_pmic0(o_output) );
fapi_try_exit:
return fapi2::current_err;
}
///
- /// @brief Decodes PMIC0 SWA Delay Sequence Order -> PMIC0_SWA_ORDER
+ /// @brief Decodes PMIC0 SWA Delay -> PMIC0_SWA_DELAY
+ /// @param[out] o_output encoding from SPD
+ /// @return FAPI2_RC_SUCCESS if okay
+ ///
+ fapi2::ReturnCode volt_delay_swa_pmic0(uint8_t& o_output) const
+ {
+ FAPI_TRY( iv_dimm_module_decoder->volt_delay_swa_pmic0(o_output) );
+
+ fapi_try_exit:
+ return fapi2::current_err;
+ }
+
+ ///
+ /// @brief Decodes PMIC0 SWA Sequence Order -> PMIC0_SWA_ORDER
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
@@ -2100,16 +2113,29 @@ class facade final
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
- fapi2::ReturnCode volt_offset_range_swb_pmic0(uint8_t& o_output) const
+ fapi2::ReturnCode volt_offset_direction_swb_pmic0(uint8_t& o_output) const
+ {
+ FAPI_TRY( iv_dimm_module_decoder->volt_offset_direction_swb_pmic0(o_output) );
+
+ fapi_try_exit:
+ return fapi2::current_err;
+ }
+
+ ///
+ /// @brief Decodes PMIC0 SWB Delay -> PMIC0_SWB_DELAY
+ /// @param[out] o_output encoding from SPD
+ /// @return FAPI2_RC_SUCCESS if okay
+ ///
+ fapi2::ReturnCode volt_delay_swb_pmic0(uint8_t& o_output) const
{
- FAPI_TRY( iv_dimm_module_decoder->volt_offset_range_swb_pmic0(o_output) );
+ FAPI_TRY( iv_dimm_module_decoder->volt_delay_swb_pmic0(o_output) );
fapi_try_exit:
return fapi2::current_err;
}
///
- /// @brief Decodes PMIC0 SWB Delay Sequence Order -> PMIC0_SWB_ORDER
+ /// @brief Decodes PMIC0 SWB Sequence Order -> PMIC0_SWB_ORDER
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
@@ -2165,16 +2191,29 @@ class facade final
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
- fapi2::ReturnCode volt_offset_range_swc_pmic0(uint8_t& o_output) const
+ fapi2::ReturnCode volt_offset_direction_swc_pmic0(uint8_t& o_output) const
{
- FAPI_TRY( iv_dimm_module_decoder->volt_offset_range_swc_pmic0(o_output) );
+ FAPI_TRY( iv_dimm_module_decoder->volt_offset_direction_swc_pmic0(o_output) );
fapi_try_exit:
return fapi2::current_err;
}
///
- /// @brief Decodes PMIC0 SWC Delay Sequence Order -> PMIC0_SWC_ORDER
+ /// @brief Decodes PMIC0 SWC Delay -> PMIC0_SWC_DELAY
+ /// @param[out] o_output encoding from SPD
+ /// @return FAPI2_RC_SUCCESS if okay
+ ///
+ fapi2::ReturnCode volt_delay_swc_pmic0(uint8_t& o_output) const
+ {
+ FAPI_TRY( iv_dimm_module_decoder->volt_delay_swc_pmic0(o_output) );
+
+ fapi_try_exit:
+ return fapi2::current_err;
+ }
+
+ ///
+ /// @brief Decodes PMIC0 SWC Sequence Order -> PMIC0_SWC_ORDER
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
@@ -2230,16 +2269,29 @@ class facade final
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
- fapi2::ReturnCode volt_offset_range_swd_pmic0(uint8_t& o_output) const
+ fapi2::ReturnCode volt_offset_direction_swd_pmic0(uint8_t& o_output) const
+ {
+ FAPI_TRY( iv_dimm_module_decoder->volt_offset_direction_swd_pmic0(o_output) );
+
+ fapi_try_exit:
+ return fapi2::current_err;
+ }
+
+ ///
+ /// @brief Decodes PMIC0 SWD Delay -> PMIC0_SWD_DELAY
+ /// @param[out] o_output encoding from SPD
+ /// @return FAPI2_RC_SUCCESS if okay
+ ///
+ fapi2::ReturnCode volt_delay_swd_pmic0(uint8_t& o_output) const
{
- FAPI_TRY( iv_dimm_module_decoder->volt_offset_range_swd_pmic0(o_output) );
+ FAPI_TRY( iv_dimm_module_decoder->volt_delay_swd_pmic0(o_output) );
fapi_try_exit:
return fapi2::current_err;
}
///
- /// @brief Decodes PMIC0 SWD Delay Sequence Order -> PMIC0_SWD_ORDER
+ /// @brief Decodes PMIC0 SWD Sequence Order -> PMIC0_SWD_ORDER
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
@@ -2308,16 +2360,29 @@ class facade final
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
- fapi2::ReturnCode volt_offset_range_swa_pmic1(uint8_t& o_output) const
+ fapi2::ReturnCode volt_offset_direction_swa_pmic1(uint8_t& o_output) const
{
- FAPI_TRY( iv_dimm_module_decoder->volt_offset_range_swa_pmic1(o_output) );
+ FAPI_TRY( iv_dimm_module_decoder->volt_offset_direction_swa_pmic1(o_output) );
fapi_try_exit:
return fapi2::current_err;
}
///
- /// @brief Decodes PMIC1 SWA Delay Sequence Order -> PMIC1_SWA_ORDER
+ /// @brief Decodes PMIC1 SWA Delay -> PMIC1_SWA_DELAY
+ /// @param[out] o_output encoding from SPD
+ /// @return FAPI2_RC_SUCCESS if okay
+ ///
+ fapi2::ReturnCode volt_delay_swa_pmic1(uint8_t& o_output) const
+ {
+ FAPI_TRY( iv_dimm_module_decoder->volt_delay_swa_pmic1(o_output) );
+
+ fapi_try_exit:
+ return fapi2::current_err;
+ }
+
+ ///
+ /// @brief Decodes PMIC1 SWA Sequence Order -> PMIC1_SWA_ORDER
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
@@ -2373,16 +2438,29 @@ class facade final
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
- fapi2::ReturnCode volt_offset_range_swb_pmic1(uint8_t& o_output) const
+ fapi2::ReturnCode volt_offset_direction_swb_pmic1(uint8_t& o_output) const
+ {
+ FAPI_TRY( iv_dimm_module_decoder->volt_offset_direction_swb_pmic1(o_output) );
+
+ fapi_try_exit:
+ return fapi2::current_err;
+ }
+
+ ///
+ /// @brief Decodes PMIC1 SWB Delay -> PMIC1_SWB_DELAY
+ /// @param[out] o_output encoding from SPD
+ /// @return FAPI2_RC_SUCCESS if okay
+ ///
+ fapi2::ReturnCode volt_delay_swb_pmic1(uint8_t& o_output) const
{
- FAPI_TRY( iv_dimm_module_decoder->volt_offset_range_swb_pmic1(o_output) );
+ FAPI_TRY( iv_dimm_module_decoder->volt_delay_swb_pmic1(o_output) );
fapi_try_exit:
return fapi2::current_err;
}
///
- /// @brief Decodes PMIC1 SWB Delay Sequence Order -> PMIC1_SWB_ORDER
+ /// @brief Decodes PMIC1 SWB Sequence Order -> PMIC1_SWB_ORDER
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
@@ -2438,16 +2516,29 @@ class facade final
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
- fapi2::ReturnCode volt_offset_range_swc_pmic1(uint8_t& o_output) const
+ fapi2::ReturnCode volt_offset_direction_swc_pmic1(uint8_t& o_output) const
{
- FAPI_TRY( iv_dimm_module_decoder->volt_offset_range_swc_pmic1(o_output) );
+ FAPI_TRY( iv_dimm_module_decoder->volt_offset_direction_swc_pmic1(o_output) );
fapi_try_exit:
return fapi2::current_err;
}
///
- /// @brief Decodes PMIC1 SWC Delay Sequence Order -> PMIC1_SWC_ORDER
+ /// @brief Decodes PMIC1 SWC Delay -> PMIC1_SWC_DELAY
+ /// @param[out] o_output encoding from SPD
+ /// @return FAPI2_RC_SUCCESS if okay
+ ///
+ fapi2::ReturnCode volt_delay_swc_pmic1(uint8_t& o_output) const
+ {
+ FAPI_TRY( iv_dimm_module_decoder->volt_delay_swc_pmic1(o_output) );
+
+ fapi_try_exit:
+ return fapi2::current_err;
+ }
+
+ ///
+ /// @brief Decodes PMIC1 SWC Sequence Order -> PMIC1_SWC_ORDER
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
@@ -2503,16 +2594,29 @@ class facade final
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
- fapi2::ReturnCode volt_offset_range_swd_pmic1(uint8_t& o_output) const
+ fapi2::ReturnCode volt_offset_direction_swd_pmic1(uint8_t& o_output) const
+ {
+ FAPI_TRY( iv_dimm_module_decoder->volt_offset_direction_swd_pmic1(o_output) );
+
+ fapi_try_exit:
+ return fapi2::current_err;
+ }
+
+ ///
+ /// @brief Decodes PMIC1 SWD Delay -> PMIC1_SWD_DELAY
+ /// @param[out] o_output encoding from SPD
+ /// @return FAPI2_RC_SUCCESS if okay
+ ///
+ fapi2::ReturnCode volt_delay_swd_pmic1(uint8_t& o_output) const
{
- FAPI_TRY( iv_dimm_module_decoder->volt_offset_range_swd_pmic1(o_output) );
+ FAPI_TRY( iv_dimm_module_decoder->volt_delay_swd_pmic1(o_output) );
fapi_try_exit:
return fapi2::current_err;
}
///
- /// @brief Decodes PMIC1 SWD Delay Sequence Order -> PMIC1_SWD_ORDER
+ /// @brief Decodes PMIC1 SWD Sequence Order -> PMIC1_SWD_ORDER
/// @param[out] o_output encoding from SPD
/// @return FAPI2_RC_SUCCESS if okay
///
diff --git a/src/import/generic/memory/lib/spd/spd_fields_ddr4.H b/src/import/generic/memory/lib/spd/spd_fields_ddr4.H
index ac110cb9d..6739276cb 100644
--- a/src/import/generic/memory/lib/spd/spd_fields_ddr4.H
+++ b/src/import/generic/memory/lib/spd/spd_fields_ddr4.H
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2018 */
+/* Contributors Listed Below - COPYRIGHT 2018,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -1003,76 +1003,84 @@ class fields<DDR4, DDIMM_MODULE>
PMIC0_SWA_VOLT_SET_BYTE = 234,
PMIC0_SWA_VOLT_SET_START = 0,
PMIC0_SWA_VOLT_SET_LEN = 7,
- PMIC0_SWA_RANGE_START = 7,
- PMIC0_SWA_RANGE_LEN = 1,
+ PMIC0_SWA_RANGE_SELECT_START = 7,
+ PMIC0_SWA_RANGE_SELECT_LEN = 1,
// Byte 235: PMIC0 SWA Voltage Offset
PMIC0_SWA_VOLT_OFF_BYTE = 235,
PMIC0_SWA_VOLT_OFF_START = 0,
PMIC0_SWA_VOLT_OFF_LEN = 7,
- PMIC0_SWA_OFF_RANGE_START = 7,
- PMIC0_SWA_OFF_RANGE_LEN = 1,
+ PMIC0_SWA_OFF_DIRECTION_START = 7,
+ PMIC0_SWA_OFF_DIRECTION_LEN = 1,
// Byte 236: PMIC0 SWA Delay Sequence Order
PMIC0_SWA_DELAY_BYTE = 236,
- PMIC0_SWA_ORDER_START = 0,
+ PMIC0_SWA_DELAY_START = 0,
+ PMIC0_SWA_DELAY_LEN = 4,
+ PMIC0_SWA_ORDER_START = 4,
PMIC0_SWA_ORDER_LEN = 4,
// Byte 237: PMIC0 SWB Voltage Setting
PMIC0_SWB_VOLT_SET_BYTE = 237,
PMIC0_SWB_VOLT_SET_START = 0,
PMIC0_SWB_VOLT_SET_LEN = 7,
- PMIC0_SWB_RANGE_START = 7,
- PMIC0_SWB_RANGE_LEN = 1,
+ PMIC0_SWB_RANGE_SELECT_START = 7,
+ PMIC0_SWB_RANGE_SELECT_LEN = 1,
// Byte 238: PMIC0 SWB Voltage Offset
PMIC0_SWB_VOLT_OFF_BYTE = 238,
PMIC0_SWB_VOLT_OFF_START = 0,
PMIC0_SWB_VOLT_OFF_LEN = 7,
- PMIC0_SWB_OFF_RANGE_START = 7,
- PMIC0_SWB_OFF_RANGE_LEN = 1,
+ PMIC0_SWB_OFF_DIRECTION_START = 7,
+ PMIC0_SWB_OFF_DIRECTION_LEN = 1,
// Byte 239: PMIC0 SWB Delay Sequence Order
PMIC0_SWB_DELAY_BYTE = 239,
- PMIC0_SWB_ORDER_START = 0,
+ PMIC0_SWB_DELAY_START = 0,
+ PMIC0_SWB_DELAY_LEN = 4,
+ PMIC0_SWB_ORDER_START = 4,
PMIC0_SWB_ORDER_LEN = 4,
// Byte 240: PMIC0 SWC Voltage Setting
PMIC0_SWC_VOLT_SET_BYTE = 240,
PMIC0_SWC_VOLT_SET_START = 0,
PMIC0_SWC_VOLT_SET_LEN = 7,
- PMIC0_SWC_RANGE_START = 7,
- PMIC0_SWC_RANGE_LEN = 1,
+ PMIC0_SWC_RANGE_SELECT_START = 7,
+ PMIC0_SWC_RANGE_SELECT_LEN = 1,
// Byte 241: PMIC0 SWC Voltage Offset
PMIC0_SWC_VOLT_OFF_BYTE = 241,
PMIC0_SWC_VOLT_OFF_START = 0,
PMIC0_SWC_VOLT_OFF_LEN = 7,
- PMIC0_SWC_OFF_RANGE_START = 7,
- PMIC0_SWC_OFF_RANGE_LEN = 1,
+ PMIC0_SWC_OFF_DIRECTION_START = 7,
+ PMIC0_SWC_OFF_DIRECTION_LEN = 1,
// Byte 242: PMIC0 SWC Delay Sequence Order
PMIC0_SWC_DELAY_BYTE = 242,
- PMIC0_SWC_ORDER_START = 0,
+ PMIC0_SWC_DELAY_START = 0,
+ PMIC0_SWC_DELAY_LEN = 4,
+ PMIC0_SWC_ORDER_START = 4,
PMIC0_SWC_ORDER_LEN = 4,
// Byte 243: PMIC0 SWD Voltage Setting
PMIC0_SWD_VOLT_SET_BYTE = 243,
PMIC0_SWD_VOLT_SET_START = 0,
PMIC0_SWD_VOLT_SET_LEN = 7,
- PMIC0_SWD_RANGE_START = 7,
- PMIC0_SWD_RANGE_LEN = 1,
+ PMIC0_SWD_RANGE_SELECT_START = 7,
+ PMIC0_SWD_RANGE_SELECT_LEN = 1,
// Byte 244: PMIC0 SWD Voltage Offset
PMIC0_SWD_VOLT_OFF_BYTE = 244,
PMIC0_SWD_VOLT_OFF_START = 0,
PMIC0_SWD_VOLT_OFF_LEN = 7,
- PMIC0_SWD_OFF_RANGE_START = 7,
- PMIC0_SWD_OFF_RANGE_LEN = 1,
+ PMIC0_SWD_OFF_DIRECTION_START = 7,
+ PMIC0_SWD_OFF_DIRECTION_LEN = 1,
// Byte 245: PMIC0 SWD Delay Sequence Order
PMIC0_SWD_DELAY_BYTE = 245,
- PMIC0_SWD_ORDER_START = 0,
+ PMIC0_SWD_DELAY_START = 0,
+ PMIC0_SWD_DELAY_LEN = 4,
+ PMIC0_SWD_ORDER_START = 4,
PMIC0_SWD_ORDER_LEN = 4,
// Byte 246: PMIC0 Phase Combination
@@ -1084,76 +1092,84 @@ class fields<DDR4, DDIMM_MODULE>
PMIC1_SWA_VOLT_SET_BYTE = 247,
PMIC1_SWA_VOLT_SET_START = 0,
PMIC1_SWA_VOLT_SET_LEN = 7,
- PMIC1_SWA_RANGE_START = 7,
- PMIC1_SWA_RANGE_LEN = 1,
+ PMIC1_SWA_RANGE_SELECT_START = 7,
+ PMIC1_SWA_RANGE_SELECT_LEN = 1,
// Byte 248: PMIC1 SWA Voltage Offset
PMIC1_SWA_VOLT_OFF_BYTE = 248,
PMIC1_SWA_VOLT_OFF_START = 0,
PMIC1_SWA_VOLT_OFF_LEN = 7,
- PMIC1_SWA_OFF_RANGE_START = 7,
- PMIC1_SWA_OFF_RANGE_LEN = 1,
+ PMIC1_SWA_OFF_DIRECTION_START = 7,
+ PMIC1_SWA_OFF_DIRECTION_LEN = 1,
// Byte 249: PMIC1 SWA Delay Sequence Order
PMIC1_SWA_DELAY_BYTE = 249,
- PMIC1_SWA_ORDER_START = 0,
+ PMIC1_SWA_DELAY_START = 0,
+ PMIC1_SWA_DELAY_LEN = 4,
+ PMIC1_SWA_ORDER_START = 4,
PMIC1_SWA_ORDER_LEN = 4,
// Byte 250: PMIC1 SWB Voltage Setting
PMIC1_SWB_VOLT_SET_BYTE = 250,
PMIC1_SWB_VOLT_SET_START = 0,
PMIC1_SWB_VOLT_SET_LEN = 7,
- PMIC1_SWB_RANGE_START = 7,
- PMIC1_SWB_RANGE_LEN = 1,
+ PMIC1_SWB_RANGE_SELECT_START = 7,
+ PMIC1_SWB_RANGE_SELECT_LEN = 1,
// Byte 251: PMIC1 SWB Voltage Offset
PMIC1_SWB_VOLT_OFF_BYTE = 251,
PMIC1_SWB_VOLT_OFF_START = 0,
PMIC1_SWB_VOLT_OFF_LEN = 7,
- PMIC1_SWB_OFF_RANGE_START = 7,
- PMIC1_SWB_OFF_RANGE_LEN = 1,
+ PMIC1_SWB_OFF_DIRECTION_START = 7,
+ PMIC1_SWB_OFF_DIRECTION_LEN = 1,
// Byte 252: PMIC1 SWB Delay Sequence Order
PMIC1_SWB_DELAY_BYTE = 252,
- PMIC1_SWB_ORDER_START = 0,
+ PMIC1_SWB_DELAY_START = 0,
+ PMIC1_SWB_DELAY_LEN = 4,
+ PMIC1_SWB_ORDER_START = 4,
PMIC1_SWB_ORDER_LEN = 4,
// Byte 253: PMIC1 SWC Voltage Setting
PMIC1_SWC_VOLT_SET_BYTE = 253,
PMIC1_SWC_VOLT_SET_START = 0,
PMIC1_SWC_VOLT_SET_LEN = 7,
- PMIC1_SWC_RANGE_START = 7,
- PMIC1_SWC_RANGE_LEN = 1,
+ PMIC1_SWC_RANGE_SELECT_START = 7,
+ PMIC1_SWC_RANGE_SELECT_LEN = 1,
// Byte 254: PMIC1 SWC Voltage Offset
PMIC1_SWC_VOLT_OFF_BYTE = 254,
PMIC1_SWC_VOLT_OFF_START = 0,
PMIC1_SWC_VOLT_OFF_LEN = 7,
- PMIC1_SWC_OFF_RANGE_START = 7,
- PMIC1_SWC_OFF_RANGE_LEN = 1,
+ PMIC1_SWC_OFF_DIRECTION_START = 7,
+ PMIC1_SWC_OFF_DIRECTION_LEN = 1,
// Byte 255: PMIC1 SWC Delay Sequence Order
PMIC1_SWC_DELAY_BYTE = 255,
- PMIC1_SWC_ORDER_START = 0,
+ PMIC1_SWC_DELAY_START = 0,
+ PMIC1_SWC_DELAY_LEN = 4,
+ PMIC1_SWC_ORDER_START = 4,
PMIC1_SWC_ORDER_LEN = 4,
// Byte 256: PMIC1 SWD Voltage Setting
PMIC1_SWD_VOLT_SET_BYTE = 256,
PMIC1_SWD_VOLT_SET_START = 0,
PMIC1_SWD_VOLT_SET_LEN = 7,
- PMIC1_SWD_RANGE_START = 7,
- PMIC1_SWD_RANGE_LEN = 1,
+ PMIC1_SWD_RANGE_SELECT_START = 7,
+ PMIC1_SWD_RANGE_SELECT_LEN = 1,
// Byte 257: PMIC1 SWD Voltage Offset
PMIC1_SWD_VOLT_OFF_BYTE = 257,
PMIC1_SWD_VOLT_OFF_START = 0,
PMIC1_SWD_VOLT_OFF_LEN = 7,
- PMIC1_SWD_OFF_RANGE_START = 7,
- PMIC1_SWD_OFF_RANGE_LEN = 1,
+ PMIC1_SWD_OFF_DIRECTION_START = 7,
+ PMIC1_SWD_OFF_DIRECTION_LEN = 1,
// Byte 258: PMIC1 SWD Delay Sequence Order
PMIC1_SWD_DELAY_BYTE = 258,
- PMIC1_SWD_ORDER_START = 0,
+ PMIC1_SWD_DELAY_START = 0,
+ PMIC1_SWD_DELAY_LEN = 4,
+ PMIC1_SWD_ORDER_START = 4,
PMIC1_SWD_ORDER_LEN = 4,
// Byte 259: PMIC1 Phase Combination
@@ -1292,46 +1308,50 @@ class fields<DDR4, DDIMM_MODULE>
// Byte 234: PMIC0 SWA Voltage Setting
static constexpr field_t PMIC0_SWA_VOLT_SET{PMIC0_SWA_VOLT_SET_BYTE, PMIC0_SWA_VOLT_SET_START, PMIC0_SWA_VOLT_SET_LEN};
- static constexpr field_t PMIC0_SWA_RANGE{PMIC0_SWA_VOLT_SET_BYTE, PMIC0_SWA_RANGE_START, PMIC0_SWA_RANGE_LEN};
+ static constexpr field_t PMIC0_SWA_RANGE_SELECT{PMIC0_SWA_VOLT_SET_BYTE, PMIC0_SWA_RANGE_SELECT_START, PMIC0_SWA_RANGE_SELECT_LEN};
// Byte 235: PMIC0 SWA Voltage Offset
static constexpr field_t PMIC0_SWA_VOLT_OFF{PMIC0_SWA_VOLT_OFF_BYTE, PMIC0_SWA_VOLT_OFF_START, PMIC0_SWA_VOLT_OFF_LEN};
- static constexpr field_t PMIC0_SWA_OFF_RANGE{PMIC0_SWA_VOLT_OFF_BYTE, PMIC0_SWA_OFF_RANGE_START, PMIC0_SWA_OFF_RANGE_LEN};
+ static constexpr field_t PMIC0_SWA_OFF_DIRECTION{PMIC0_SWA_VOLT_OFF_BYTE, PMIC0_SWA_OFF_DIRECTION_START, PMIC0_SWA_OFF_DIRECTION_LEN};
// Byte 236: PMIC0 SWA Delay Sequence Order
+ static constexpr field_t PMIC0_SWA_DELAY{PMIC0_SWA_DELAY_BYTE, PMIC0_SWA_DELAY_START, PMIC0_SWA_DELAY_LEN};
static constexpr field_t PMIC0_SWA_ORDER{PMIC0_SWA_DELAY_BYTE, PMIC0_SWA_ORDER_START, PMIC0_SWA_ORDER_LEN};
// Byte 237: PMIC0 SWB Voltage Setting
static constexpr field_t PMIC0_SWB_VOLT_SET{PMIC0_SWB_VOLT_SET_BYTE, PMIC0_SWB_VOLT_SET_START, PMIC0_SWB_VOLT_SET_LEN};
- static constexpr field_t PMIC0_SWB_RANGE{PMIC0_SWB_VOLT_SET_BYTE, PMIC0_SWB_RANGE_START, PMIC0_SWB_RANGE_LEN};
+ static constexpr field_t PMIC0_SWB_RANGE_SELECT{PMIC0_SWB_VOLT_SET_BYTE, PMIC0_SWB_RANGE_SELECT_START, PMIC0_SWB_RANGE_SELECT_LEN};
// Byte 238: PMIC0 SWB Voltage Offset
static constexpr field_t PMIC0_SWB_VOLT_OFF{PMIC0_SWB_VOLT_OFF_BYTE, PMIC0_SWB_VOLT_OFF_START, PMIC0_SWB_VOLT_OFF_LEN};
- static constexpr field_t PMIC0_SWB_OFF_RANGE{PMIC0_SWB_VOLT_OFF_BYTE, PMIC0_SWB_OFF_RANGE_START, PMIC0_SWB_OFF_RANGE_LEN};
+ static constexpr field_t PMIC0_SWB_OFF_DIRECTION{PMIC0_SWB_VOLT_OFF_BYTE, PMIC0_SWB_OFF_DIRECTION_START, PMIC0_SWB_OFF_DIRECTION_LEN};
// Byte 239: PMIC0 SWB Delay Sequence Order
+ static constexpr field_t PMIC0_SWB_DELAY{PMIC0_SWB_DELAY_BYTE, PMIC0_SWB_DELAY_START, PMIC0_SWB_DELAY_LEN};
static constexpr field_t PMIC0_SWB_ORDER{PMIC0_SWB_DELAY_BYTE, PMIC0_SWB_ORDER_START, PMIC0_SWB_ORDER_LEN};
// Byte 240: PMIC0 SWC Voltage Setting
static constexpr field_t PMIC0_SWC_VOLT_SET{PMIC0_SWC_VOLT_SET_BYTE, PMIC0_SWC_VOLT_SET_START, PMIC0_SWC_VOLT_SET_LEN};
- static constexpr field_t PMIC0_SWC_RANGE{PMIC0_SWC_VOLT_SET_BYTE, PMIC0_SWC_RANGE_START, PMIC0_SWC_RANGE_LEN};
+ static constexpr field_t PMIC0_SWC_RANGE_SELECT{PMIC0_SWC_VOLT_SET_BYTE, PMIC0_SWC_RANGE_SELECT_START, PMIC0_SWC_RANGE_SELECT_LEN};
// Byte 241: PMIC0 SWC Voltage Offset
static constexpr field_t PMIC0_SWC_VOLT_OFF{PMIC0_SWC_VOLT_OFF_BYTE, PMIC0_SWC_VOLT_OFF_START, PMIC0_SWC_VOLT_OFF_LEN};
- static constexpr field_t PMIC0_SWC_OFF_RANGE{PMIC0_SWC_VOLT_OFF_BYTE, PMIC0_SWC_OFF_RANGE_START, PMIC0_SWC_OFF_RANGE_LEN};
+ static constexpr field_t PMIC0_SWC_OFF_DIRECTION{PMIC0_SWC_VOLT_OFF_BYTE, PMIC0_SWC_OFF_DIRECTION_START, PMIC0_SWC_OFF_DIRECTION_LEN};
// Byte 242: PMIC0 SWC Delay Sequence Order
+ static constexpr field_t PMIC0_SWC_DELAY{PMIC0_SWC_DELAY_BYTE, PMIC0_SWC_DELAY_START, PMIC0_SWC_DELAY_LEN};
static constexpr field_t PMIC0_SWC_ORDER{PMIC0_SWC_DELAY_BYTE, PMIC0_SWC_ORDER_START, PMIC0_SWC_ORDER_LEN};
// Byte 243: PMIC0 SWD Voltage Setting
static constexpr field_t PMIC0_SWD_VOLT_SET{PMIC0_SWD_VOLT_SET_BYTE, PMIC0_SWD_VOLT_SET_START, PMIC0_SWD_VOLT_SET_LEN};
- static constexpr field_t PMIC0_SWD_RANGE{PMIC0_SWD_VOLT_SET_BYTE, PMIC0_SWD_RANGE_START, PMIC0_SWD_RANGE_LEN};
+ static constexpr field_t PMIC0_SWD_RANGE_SELECT{PMIC0_SWD_VOLT_SET_BYTE, PMIC0_SWD_RANGE_SELECT_START, PMIC0_SWD_RANGE_SELECT_LEN};
// Byte 244: PMIC0 SWD Voltage Offset
static constexpr field_t PMIC0_SWD_VOLT_OFF{PMIC0_SWD_VOLT_OFF_BYTE, PMIC0_SWD_VOLT_OFF_START, PMIC0_SWD_VOLT_OFF_LEN};
- static constexpr field_t PMIC0_SWD_OFF_RANGE{PMIC0_SWD_VOLT_OFF_BYTE, PMIC0_SWD_OFF_RANGE_START, PMIC0_SWD_OFF_RANGE_LEN};
+ static constexpr field_t PMIC0_SWD_OFF_DIRECTION{PMIC0_SWD_VOLT_OFF_BYTE, PMIC0_SWD_OFF_DIRECTION_START, PMIC0_SWD_OFF_DIRECTION_LEN};
// Byte 245: PMIC0 SWD Delay Sequence Order
+ static constexpr field_t PMIC0_SWD_DELAY{PMIC0_SWD_DELAY_BYTE, PMIC0_SWD_DELAY_START, PMIC0_SWD_DELAY_LEN};
static constexpr field_t PMIC0_SWD_ORDER{PMIC0_SWD_DELAY_BYTE, PMIC0_SWD_ORDER_START, PMIC0_SWD_ORDER_LEN};
// Byte 246: PMIC0 Phase Combination
@@ -1339,46 +1359,50 @@ class fields<DDR4, DDIMM_MODULE>
// Byte 247: PMIC1 SWA Voltage Setting
static constexpr field_t PMIC1_SWA_VOLT_SET{PMIC1_SWA_VOLT_SET_BYTE, PMIC1_SWA_VOLT_SET_START, PMIC1_SWA_VOLT_SET_LEN};
- static constexpr field_t PMIC1_SWA_RANGE{PMIC1_SWA_VOLT_SET_BYTE, PMIC1_SWA_RANGE_START, PMIC1_SWA_RANGE_LEN};
+ static constexpr field_t PMIC1_SWA_RANGE_SELECT{PMIC1_SWA_VOLT_SET_BYTE, PMIC1_SWA_RANGE_SELECT_START, PMIC1_SWA_RANGE_SELECT_LEN};
// Byte 248: PMIC1 SWA Voltage Offset
static constexpr field_t PMIC1_SWA_VOLT_OFF{PMIC1_SWA_VOLT_OFF_BYTE, PMIC1_SWA_VOLT_OFF_START, PMIC1_SWA_VOLT_OFF_LEN};
- static constexpr field_t PMIC1_SWA_OFF_RANGE{PMIC1_SWA_VOLT_OFF_BYTE, PMIC1_SWA_OFF_RANGE_START, PMIC1_SWA_OFF_RANGE_LEN};
+ static constexpr field_t PMIC1_SWA_OFF_DIRECTION{PMIC1_SWA_VOLT_OFF_BYTE, PMIC1_SWA_OFF_DIRECTION_START, PMIC1_SWA_OFF_DIRECTION_LEN};
// Byte 249: PMIC1 SWA Delay Sequence Order
+ static constexpr field_t PMIC1_SWA_DELAY{PMIC1_SWA_DELAY_BYTE, PMIC1_SWA_DELAY_START, PMIC1_SWA_DELAY_LEN};
static constexpr field_t PMIC1_SWA_ORDER{PMIC1_SWA_DELAY_BYTE, PMIC1_SWA_ORDER_START, PMIC1_SWA_ORDER_LEN};
// Byte 250: PMIC1 SWB Voltage Setting
static constexpr field_t PMIC1_SWB_VOLT_SET{PMIC1_SWB_VOLT_SET_BYTE, PMIC1_SWB_VOLT_SET_START, PMIC1_SWB_VOLT_SET_LEN};
- static constexpr field_t PMIC1_SWB_RANGE{PMIC1_SWB_VOLT_SET_BYTE, PMIC1_SWB_RANGE_START, PMIC1_SWB_RANGE_LEN};
+ static constexpr field_t PMIC1_SWB_RANGE_SELECT{PMIC1_SWB_VOLT_SET_BYTE, PMIC1_SWB_RANGE_SELECT_START, PMIC1_SWB_RANGE_SELECT_LEN};
// Byte 251: PMIC1 SWB Voltage Offset
static constexpr field_t PMIC1_SWB_VOLT_OFF{PMIC1_SWB_VOLT_OFF_BYTE, PMIC1_SWB_VOLT_OFF_START, PMIC1_SWB_VOLT_OFF_LEN};
- static constexpr field_t PMIC1_SWB_OFF_RANGE{PMIC1_SWB_VOLT_OFF_BYTE, PMIC1_SWB_OFF_RANGE_START, PMIC1_SWB_OFF_RANGE_LEN};
+ static constexpr field_t PMIC1_SWB_OFF_DIRECTION{PMIC1_SWB_VOLT_OFF_BYTE, PMIC1_SWB_OFF_DIRECTION_START, PMIC1_SWB_OFF_DIRECTION_LEN};
// Byte 252: PMIC1 SWB Delay Sequence Order
+ static constexpr field_t PMIC1_SWB_DELAY{PMIC1_SWB_DELAY_BYTE, PMIC1_SWB_DELAY_START, PMIC1_SWB_DELAY_LEN};
static constexpr field_t PMIC1_SWB_ORDER{PMIC1_SWB_DELAY_BYTE, PMIC1_SWB_ORDER_START, PMIC1_SWB_ORDER_LEN};
// Byte 253: PMIC1 SWC Voltage Setting
static constexpr field_t PMIC1_SWC_VOLT_SET{PMIC1_SWC_VOLT_SET_BYTE, PMIC1_SWC_VOLT_SET_START, PMIC1_SWC_VOLT_SET_LEN};
- static constexpr field_t PMIC1_SWC_RANGE{PMIC1_SWC_VOLT_SET_BYTE, PMIC1_SWC_RANGE_START, PMIC1_SWC_RANGE_LEN};
+ static constexpr field_t PMIC1_SWC_RANGE_SELECT{PMIC1_SWC_VOLT_SET_BYTE, PMIC1_SWC_RANGE_SELECT_START, PMIC1_SWC_RANGE_SELECT_LEN};
// Byte 254: PMIC1 SWC Voltage Offset
static constexpr field_t PMIC1_SWC_VOLT_OFF{PMIC1_SWC_VOLT_OFF_BYTE, PMIC1_SWC_VOLT_OFF_START, PMIC1_SWC_VOLT_OFF_LEN};
- static constexpr field_t PMIC1_SWC_OFF_RANGE{PMIC1_SWC_VOLT_OFF_BYTE, PMIC1_SWC_OFF_RANGE_START, PMIC1_SWC_OFF_RANGE_LEN};
+ static constexpr field_t PMIC1_SWC_OFF_DIRECTION{PMIC1_SWC_VOLT_OFF_BYTE, PMIC1_SWC_OFF_DIRECTION_START, PMIC1_SWC_OFF_DIRECTION_LEN};
// Byte 255: PMIC1 SWC Delay Sequence Order
+ static constexpr field_t PMIC1_SWC_DELAY{PMIC1_SWC_DELAY_BYTE, PMIC1_SWC_DELAY_START, PMIC1_SWC_DELAY_LEN};
static constexpr field_t PMIC1_SWC_ORDER{PMIC1_SWC_DELAY_BYTE, PMIC1_SWC_ORDER_START, PMIC1_SWC_ORDER_LEN};
// Byte 256: PMIC1 SWD Voltage Setting
static constexpr field_t PMIC1_SWD_VOLT_SET{PMIC1_SWD_VOLT_SET_BYTE, PMIC1_SWD_VOLT_SET_START, PMIC1_SWD_VOLT_SET_LEN};
- static constexpr field_t PMIC1_SWD_RANGE{PMIC1_SWD_VOLT_SET_BYTE, PMIC1_SWD_RANGE_START, PMIC1_SWD_RANGE_LEN};
+ static constexpr field_t PMIC1_SWD_RANGE_SELECT{PMIC1_SWD_VOLT_SET_BYTE, PMIC1_SWD_RANGE_SELECT_START, PMIC1_SWD_RANGE_SELECT_LEN};
// Byte 257: PMIC1 SWD Voltage Offset
static constexpr field_t PMIC1_SWD_VOLT_OFF{PMIC1_SWD_VOLT_OFF_BYTE, PMIC1_SWD_VOLT_OFF_START, PMIC1_SWD_VOLT_OFF_LEN};
- static constexpr field_t PMIC1_SWD_OFF_RANGE{PMIC1_SWD_VOLT_OFF_BYTE, PMIC1_SWD_OFF_RANGE_START, PMIC1_SWD_OFF_RANGE_LEN};
+ static constexpr field_t PMIC1_SWD_OFF_DIRECTION{PMIC1_SWD_VOLT_OFF_BYTE, PMIC1_SWD_OFF_DIRECTION_START, PMIC1_SWD_OFF_DIRECTION_LEN};
// Byte 258: PMIC1 SWD Delay Sequence Order
+ static constexpr field_t PMIC1_SWD_DELAY{PMIC1_SWD_DELAY_BYTE, PMIC1_SWD_DELAY_START, PMIC1_SWD_DELAY_LEN};
static constexpr field_t PMIC1_SWD_ORDER{PMIC1_SWD_DELAY_BYTE, PMIC1_SWD_ORDER_START, PMIC1_SWD_ORDER_LEN};
// Byte 259: PMIC1 Phase Combination
diff --git a/src/import/generic/memory/lib/spd/spd_traits_ddr4.H b/src/import/generic/memory/lib/spd/spd_traits_ddr4.H
index c26ca2082..ecdaec291 100644
--- a/src/import/generic/memory/lib/spd/spd_traits_ddr4.H
+++ b/src/import/generic/memory/lib/spd/spd_traits_ddr4.H
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2018 */
+/* Contributors Listed Below - COPYRIGHT 2018,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -4621,11 +4621,11 @@ class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC0_SWA_VOLT_SET, R >
/// @class readerTraits
/// @brief trait structure to hold static SPD information
/// @tparam R the revision of the SPD field
-/// @note PMIC0_SWA_RANGE field specialization
+/// @note PMIC0_SWA_RANGE_SELECT field specialization
/// @note valid for all revs
///
template< rev R >
-class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC0_SWA_RANGE, R >
+class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC0_SWA_RANGE_SELECT, R >
{
public:
@@ -4659,16 +4659,35 @@ class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC0_SWA_VOLT_OFF, R >
/// @class readerTraits
/// @brief trait structure to hold static SPD information
/// @tparam R the revision of the SPD field
-/// @note PMIC0_SWA_OFF_RANGE field specialization
+/// @note PMIC0_SWA_OFF_DIRECTION field specialization
/// @note valid for all revs
///
template< rev R >
-class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC0_SWA_OFF_RANGE, R >
+class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC0_SWA_OFF_DIRECTION, R >
{
public:
static constexpr size_t COMPARISON_VAL = 0x01;
- static constexpr const char* FIELD_STR = "PMIC0 SWA Voltage Offset Range";
+ static constexpr const char* FIELD_STR = "PMIC0 SWA Voltage Offset Direction";
+
+ template <typename T>
+ using COMPARISON_OP = std::less_equal<T>;
+};
+
+///
+/// @class readerTraits
+/// @brief trait structure to hold static SPD information
+/// @tparam R the revision of the SPD field
+/// @note PMIC0_SWA_DELAY field specialization
+/// @note valid for all revs
+///
+template< rev R >
+class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC0_SWA_DELAY, R >
+{
+ public:
+
+ static constexpr size_t COMPARISON_VAL = 0x07;
+ static constexpr const char* FIELD_STR = "PMIC0 SWA Delay";
template <typename T>
using COMPARISON_OP = std::less_equal<T>;
@@ -4716,11 +4735,11 @@ class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC0_SWB_VOLT_SET, R >
/// @class readerTraits
/// @brief trait structure to hold static SPD information
/// @tparam R the revision of the SPD field
-/// @note PMIC0_SWB_RANGE field specialization
+/// @note PMIC0_SWB_RANGE_SELECT field specialization
/// @note valid for all revs
///
template< rev R >
-class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC0_SWB_RANGE, R >
+class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC0_SWB_RANGE_SELECT, R >
{
public:
@@ -4754,16 +4773,16 @@ class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC0_SWB_VOLT_OFF, R >
/// @class readerTraits
/// @brief trait structure to hold static SPD information
/// @tparam R the revision of the SPD field
-/// @note PMIC0_SWB_OFF_RANGE field specialization
+/// @note PMIC0_SWB_OFF_DIRECTION field specialization
/// @note valid for all revs
///
template< rev R >
-class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC0_SWB_OFF_RANGE, R >
+class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC0_SWB_OFF_DIRECTION, R >
{
public:
static constexpr size_t COMPARISON_VAL = 0x01;
- static constexpr const char* FIELD_STR = "PMIC0 SWB Voltage Offset Range";
+ static constexpr const char* FIELD_STR = "PMIC0 SWB Voltage Offset Direction";
template <typename T>
using COMPARISON_OP = std::less_equal<T>;
@@ -4773,6 +4792,26 @@ class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC0_SWB_OFF_RANGE, R >
/// @class readerTraits
/// @brief trait structure to hold static SPD information
/// @tparam R the revision of the SPD field
+/// @note PMIC0_SWB_DELAY field specialization
+/// @note valid for all revs
+///
+template< rev R >
+class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC0_SWB_DELAY, R >
+{
+ public:
+
+ static constexpr size_t COMPARISON_VAL = 0x07;
+ static constexpr const char* FIELD_STR = "PMIC0 SWB Delay";
+
+ template <typename T>
+ using COMPARISON_OP = std::less_equal<T>;
+};
+
+
+///
+/// @class readerTraits
+/// @brief trait structure to hold static SPD information
+/// @tparam R the revision of the SPD field
/// @note PMIC0_SWB_ORDER field specialization
/// @note valid for all revs
///
@@ -4811,11 +4850,11 @@ class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC0_SWC_VOLT_SET, R >
/// @class readerTraits
/// @brief trait structure to hold static SPD information
/// @tparam R the revision of the SPD field
-/// @note PMIC0_SWC_RANGE field specialization
+/// @note PMIC0_SWC_RANGE_SELECT field specialization
/// @note valid for all revs
///
template< rev R >
-class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC0_SWC_RANGE, R >
+class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC0_SWC_RANGE_SELECT, R >
{
public:
@@ -4849,16 +4888,16 @@ class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC0_SWC_VOLT_OFF, R >
/// @class readerTraits
/// @brief trait structure to hold static SPD information
/// @tparam R the revision of the SPD field
-/// @note PMIC0_SWC_OFF_RANGE field specialization
+/// @note PMIC0_SWC_OFF_DIRECTION field specialization
/// @note valid for all revs
///
template< rev R >
-class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC0_SWC_OFF_RANGE, R >
+class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC0_SWC_OFF_DIRECTION, R >
{
public:
static constexpr size_t COMPARISON_VAL = 0x01;
- static constexpr const char* FIELD_STR = "PMIC0 SWC Voltage Offset Range";
+ static constexpr const char* FIELD_STR = "PMIC0 SWC Voltage Offset Direction";
template <typename T>
using COMPARISON_OP = std::less_equal<T>;
@@ -4868,6 +4907,26 @@ class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC0_SWC_OFF_RANGE, R >
/// @class readerTraits
/// @brief trait structure to hold static SPD information
/// @tparam R the revision of the SPD field
+/// @note PMIC0_SWC_DELAY field specialization
+/// @note valid for all revs
+///
+template< rev R >
+class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC0_SWC_DELAY, R >
+{
+ public:
+
+ static constexpr size_t COMPARISON_VAL = 0x07;
+ static constexpr const char* FIELD_STR = "PMIC0 SWC Delay";
+
+ template <typename T>
+ using COMPARISON_OP = std::less_equal<T>;
+};
+
+
+///
+/// @class readerTraits
+/// @brief trait structure to hold static SPD information
+/// @tparam R the revision of the SPD field
/// @note PMIC0_SWC_ORDER field specialization
/// @note valid for all revs
///
@@ -4906,11 +4965,11 @@ class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC0_SWD_VOLT_SET, R >
/// @class readerTraits
/// @brief trait structure to hold static SPD information
/// @tparam R the revision of the SPD field
-/// @note PMIC0_SWD_RANGE field specialization
+/// @note PMIC0_SWD_RANGE_SELECT field specialization
/// @note valid for all revs
///
template< rev R >
-class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC0_SWD_RANGE, R >
+class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC0_SWD_RANGE_SELECT, R >
{
public:
@@ -4944,16 +5003,16 @@ class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC0_SWD_VOLT_OFF, R >
/// @class readerTraits
/// @brief trait structure to hold static SPD information
/// @tparam R the revision of the SPD field
-/// @note PMIC0_SWD_OFF_RANGE field specialization
+/// @note PMIC0_SWD_OFF_DIRECTION field specialization
/// @note valid for all revs
///
template< rev R >
-class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC0_SWD_OFF_RANGE, R >
+class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC0_SWD_OFF_DIRECTION, R >
{
public:
static constexpr size_t COMPARISON_VAL = 0x01;
- static constexpr const char* FIELD_STR = "PMIC0 SWD Voltage Offset Range";
+ static constexpr const char* FIELD_STR = "PMIC0 SWD Voltage Offset Direction";
template <typename T>
using COMPARISON_OP = std::less_equal<T>;
@@ -4963,6 +5022,26 @@ class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC0_SWD_OFF_RANGE, R >
/// @class readerTraits
/// @brief trait structure to hold static SPD information
/// @tparam R the revision of the SPD field
+/// @note PMIC0_SWD_DELAY field specialization
+/// @note valid for all revs
+///
+template< rev R >
+class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC0_SWD_DELAY, R >
+{
+ public:
+
+ static constexpr size_t COMPARISON_VAL = 0x07;
+ static constexpr const char* FIELD_STR = "PMIC0 SWD Delay";
+
+ template <typename T>
+ using COMPARISON_OP = std::less_equal<T>;
+};
+
+
+///
+/// @class readerTraits
+/// @brief trait structure to hold static SPD information
+/// @tparam R the revision of the SPD field
/// @note PMIC0_SWD_ORDER field specialization
/// @note valid for all revs
///
@@ -5020,11 +5099,11 @@ class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC1_SWA_VOLT_SET, R >
/// @class readerTraits
/// @brief trait structure to hold static SPD information
/// @tparam R the revision of the SPD field
-/// @note PMIC1_SWA_RANGE field specialization
+/// @note PMIC1_SWA_RANGE_SELECT field specialization
/// @note valid for all revs
///
template< rev R >
-class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC1_SWA_RANGE, R >
+class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC1_SWA_RANGE_SELECT, R >
{
public:
@@ -5058,16 +5137,35 @@ class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC1_SWA_VOLT_OFF, R >
/// @class readerTraits
/// @brief trait structure to hold static SPD information
/// @tparam R the revision of the SPD field
-/// @note PMIC1_SWA_OFF_RANGE field specialization
+/// @note PMIC1_SWA_OFF_DIRECTION field specialization
/// @note valid for all revs
///
template< rev R >
-class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC1_SWA_OFF_RANGE, R >
+class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC1_SWA_OFF_DIRECTION, R >
{
public:
static constexpr size_t COMPARISON_VAL = 0x01;
- static constexpr const char* FIELD_STR = "PMIC1 SWA Voltage Offset Range";
+ static constexpr const char* FIELD_STR = "PMIC1 SWA Voltage Offset Direction";
+
+ template <typename T>
+ using COMPARISON_OP = std::less_equal<T>;
+};
+
+///
+/// @class readerTraits
+/// @brief trait structure to hold static SPD information
+/// @tparam R the revision of the SPD field
+/// @note PMIC1_SWA_DELAY field specialization
+/// @note valid for all revs
+///
+template< rev R >
+class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC1_SWA_DELAY, R >
+{
+ public:
+
+ static constexpr size_t COMPARISON_VAL = 0x07;
+ static constexpr const char* FIELD_STR = "PMIC1 SWA Delay";
template <typename T>
using COMPARISON_OP = std::less_equal<T>;
@@ -5115,11 +5213,11 @@ class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC1_SWB_VOLT_SET, R >
/// @class readerTraits
/// @brief trait structure to hold static SPD information
/// @tparam R the revision of the SPD field
-/// @note PMIC1_SWB_RANGE field specialization
+/// @note PMIC1_SWB_RANGE_SELECT field specialization
/// @note valid for all revs
///
template< rev R >
-class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC1_SWB_RANGE, R >
+class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC1_SWB_RANGE_SELECT, R >
{
public:
@@ -5153,16 +5251,35 @@ class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC1_SWB_VOLT_OFF, R >
/// @class readerTraits
/// @brief trait structure to hold static SPD information
/// @tparam R the revision of the SPD field
-/// @note PMIC1_SWB_OFF_RANGE field specialization
+/// @note PMIC1_SWB_OFF_DIRECTION field specialization
/// @note valid for all revs
///
template< rev R >
-class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC1_SWB_OFF_RANGE, R >
+class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC1_SWB_OFF_DIRECTION, R >
{
public:
static constexpr size_t COMPARISON_VAL = 0x01;
- static constexpr const char* FIELD_STR = "PMIC1 SWB Voltage Offset Range";
+ static constexpr const char* FIELD_STR = "PMIC1 SWB Voltage Offset Direction";
+
+ template <typename T>
+ using COMPARISON_OP = std::less_equal<T>;
+};
+
+///
+/// @class readerTraits
+/// @brief trait structure to hold static SPD information
+/// @tparam R the revision of the SPD field
+/// @note PMIC1_SWB_DELAY field specialization
+/// @note valid for all revs
+///
+template< rev R >
+class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC1_SWB_DELAY, R >
+{
+ public:
+
+ static constexpr size_t COMPARISON_VAL = 0x07;
+ static constexpr const char* FIELD_STR = "PMIC1 SWB Delay";
template <typename T>
using COMPARISON_OP = std::less_equal<T>;
@@ -5210,11 +5327,11 @@ class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC1_SWC_VOLT_SET, R >
/// @class readerTraits
/// @brief trait structure to hold static SPD information
/// @tparam R the revision of the SPD field
-/// @note PMIC1_SWC_RANGE field specialization
+/// @note PMIC1_SWC_RANGE_SELECT field specialization
/// @note valid for all revs
///
template< rev R >
-class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC1_SWC_RANGE, R >
+class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC1_SWC_RANGE_SELECT, R >
{
public:
@@ -5248,16 +5365,35 @@ class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC1_SWC_VOLT_OFF, R >
/// @class readerTraits
/// @brief trait structure to hold static SPD information
/// @tparam R the revision of the SPD field
-/// @note PMIC1_SWC_OFF_RANGE field specialization
+/// @note PMIC1_SWC_OFF_DIRECTION field specialization
/// @note valid for all revs
///
template< rev R >
-class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC1_SWC_OFF_RANGE, R >
+class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC1_SWC_OFF_DIRECTION, R >
{
public:
static constexpr size_t COMPARISON_VAL = 0x01;
- static constexpr const char* FIELD_STR = "PMIC1 SWC Voltage Offset Range";
+ static constexpr const char* FIELD_STR = "PMIC1 SWC Voltage Offset Direction";
+
+ template <typename T>
+ using COMPARISON_OP = std::less_equal<T>;
+};
+
+///
+/// @class readerTraits
+/// @brief trait structure to hold static SPD information
+/// @tparam R the revision of the SPD field
+/// @note PMIC1_SWC_DELAY field specialization
+/// @note valid for all revs
+///
+template< rev R >
+class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC1_SWC_DELAY, R >
+{
+ public:
+
+ static constexpr size_t COMPARISON_VAL = 0x07;
+ static constexpr const char* FIELD_STR = "PMIC1 SWC Delay";
template <typename T>
using COMPARISON_OP = std::less_equal<T>;
@@ -5305,11 +5441,11 @@ class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC1_SWD_VOLT_SET, R >
/// @class readerTraits
/// @brief trait structure to hold static SPD information
/// @tparam R the revision of the SPD field
-/// @note PMIC1_SWD_RANGE field specialization
+/// @note PMIC1_SWD_RANGE_SELECT field specialization
/// @note valid for all revs
///
template< rev R >
-class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC1_SWD_RANGE, R >
+class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC1_SWD_RANGE_SELECT, R >
{
public:
@@ -5343,16 +5479,35 @@ class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC1_SWD_VOLT_OFF, R >
/// @class readerTraits
/// @brief trait structure to hold static SPD information
/// @tparam R the revision of the SPD field
-/// @note PMIC1_SWD_OFF_RANGE field specialization
+/// @note PMIC1_SWD_OFF_DIRECTION field specialization
/// @note valid for all revs
///
template< rev R >
-class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC1_SWD_OFF_RANGE, R >
+class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC1_SWD_OFF_DIRECTION, R >
{
public:
static constexpr size_t COMPARISON_VAL = 0x01;
- static constexpr const char* FIELD_STR = "PMIC1 SWD Voltage Offset Range";
+ static constexpr const char* FIELD_STR = "PMIC1 SWD Voltage Offset Direction";
+
+ template <typename T>
+ using COMPARISON_OP = std::less_equal<T>;
+};
+
+///
+/// @class readerTraits
+/// @brief trait structure to hold static SPD information
+/// @tparam R the revision of the SPD field
+/// @note PMIC1_SWD_DELAY field specialization
+/// @note valid for all revs
+///
+template< rev R >
+class readerTraits < fields< DDR4, DDIMM_MODULE>::PMIC1_SWD_DELAY, R >
+{
+ public:
+
+ static constexpr size_t COMPARISON_VAL = 0x07;
+ static constexpr const char* FIELD_STR = "PMIC1 SWD Delay";
template <typename T>
using COMPARISON_OP = std::less_equal<T>;
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