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| author | Andre Marin <aamarin@us.ibm.com> | 2017-04-05 09:18:27 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-04-10 15:37:04 -0400 |
| commit | 8df4bc28dd0a5618c8ad9c9cec1812cf0f065e8e (patch) | |
| tree | 81de27b3c5157059654f51b353d0e7f5f5638349 /src/import/generic/memory/lib/spd/common | |
| parent | 3b5685fd65c0ab8720dfa8c8562e99463326b816 (diff) | |
| download | talos-hostboot-8df4bc28dd0a5618c8ad9c9cec1812cf0f065e8e.tar.gz talos-hostboot-8df4bc28dd0a5618c8ad9c9cec1812cf0f065e8e.zip | |
Add const to the end of spd decoder methods to denote unchanged mem vars
Change-Id: I6be84549a46484d9d3d4ad3212e624b4cbbd6e07
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38875
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38880
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/generic/memory/lib/spd/common')
5 files changed, 276 insertions, 276 deletions
diff --git a/src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H b/src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H index 61d3eb476..63584075f 100644 --- a/src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H +++ b/src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H @@ -333,7 +333,7 @@ class decoder_v1_0 : public decoder /// @param[out] o_logical_ranks number of logical ranks /// @return fapi2::FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode prim_sdram_logical_ranks( uint8_t& o_logical_ranks ); + virtual fapi2::ReturnCode prim_sdram_logical_ranks( uint8_t& o_logical_ranks ) const; public: @@ -425,7 +425,7 @@ class decoder_v1_0 : public decoder /// @note Page 14 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode number_of_used_bytes( uint16_t& o_value ) override; + virtual fapi2::ReturnCode number_of_used_bytes( uint16_t& o_value ) const override; /// /// @brief Decodes total number of SPD bytes @@ -436,7 +436,7 @@ class decoder_v1_0 : public decoder /// @note Page 14 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode number_of_total_bytes( uint16_t& o_value ) override; + virtual fapi2::ReturnCode number_of_total_bytes( uint16_t& o_value ) const override; /// /// @brief Decodes hybrid media field from SPD @@ -447,7 +447,7 @@ class decoder_v1_0 : public decoder /// @note Page 17 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode hybrid_media( uint8_t& o_value ) override; + virtual fapi2::ReturnCode hybrid_media( uint8_t& o_value ) const override; /// /// @brief Decodes hybrid field from SPD @@ -458,7 +458,7 @@ class decoder_v1_0 : public decoder /// @note Page 17 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode hybrid( uint8_t& o_value ) override; + virtual fapi2::ReturnCode hybrid( uint8_t& o_value ) const override; /// /// @brief Decodes SDRAM density from SPD @@ -469,7 +469,7 @@ class decoder_v1_0 : public decoder /// @note Page 18 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode sdram_density( uint8_t& o_value ) override; + virtual fapi2::ReturnCode sdram_density( uint8_t& o_value ) const override; /// /// @brief Decodes number of SDRAM banks bits from SPD @@ -480,7 +480,7 @@ class decoder_v1_0 : public decoder /// @note Page 18 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode bank_bits( uint8_t& o_value ) override; + virtual fapi2::ReturnCode bank_bits( uint8_t& o_value ) const override; /// /// @brief Decodes number of SDRAM bank groups bits from SPD @@ -491,7 +491,7 @@ class decoder_v1_0 : public decoder /// @note Page 18 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode bank_group_bits( uint8_t& o_value ) override; + virtual fapi2::ReturnCode bank_group_bits( uint8_t& o_value ) const override; /// /// @brief Decodes number of SDRAM column address bits @@ -501,7 +501,7 @@ class decoder_v1_0 : public decoder /// @note Page 18 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode column_address_bits( uint8_t& o_value ) override; + virtual fapi2::ReturnCode column_address_bits( uint8_t& o_value ) const override; /// /// @brief Decodes number of SDRAM row address bits @@ -511,7 +511,7 @@ class decoder_v1_0 : public decoder /// @note Page 18 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode row_address_bits( uint8_t& o_value ) override; + virtual fapi2::ReturnCode row_address_bits( uint8_t& o_value ) const override; /// /// @brief Decodes Primary SDRAM signal loading @@ -521,7 +521,7 @@ class decoder_v1_0 : public decoder /// @note Page 19 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode prim_sdram_signal_loading( uint8_t& o_value ) override; + virtual fapi2::ReturnCode prim_sdram_signal_loading( uint8_t& o_value ) const override; /// /// @brief Decodes Primary SDRAM die count @@ -531,7 +531,7 @@ class decoder_v1_0 : public decoder /// @note Page 19 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode prim_sdram_die_count( uint8_t& o_value ) override; + virtual fapi2::ReturnCode prim_sdram_die_count( uint8_t& o_value ) const override; /// /// @brief Decodes Primary SDRAM package type @@ -541,7 +541,7 @@ class decoder_v1_0 : public decoder /// @note Page 19 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode prim_sdram_package_type( uint8_t& o_value ) override; + virtual fapi2::ReturnCode prim_sdram_package_type( uint8_t& o_value ) const override; /// /// @brief Decode SDRAM Maximum activate count @@ -551,7 +551,7 @@ class decoder_v1_0 : public decoder /// @note Page 20 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode maximum_activate_count( uint32_t& o_value ) override; + virtual fapi2::ReturnCode maximum_activate_count( uint32_t& o_value ) const override; /// /// @brief Decode SDRAM Maximum activate window (multiplier), tREFI uknown at this point @@ -561,7 +561,7 @@ class decoder_v1_0 : public decoder /// @note Page 20 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode maximum_activate_window_multiplier( uint32_t& o_value ) override; + virtual fapi2::ReturnCode maximum_activate_window_multiplier( uint32_t& o_value ) const override; /// /// @brief Decode Post package repair (PPR) @@ -571,7 +571,7 @@ class decoder_v1_0 : public decoder /// @note Page 21 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode post_package_repair( uint8_t& o_value ) override; + virtual fapi2::ReturnCode post_package_repair( uint8_t& o_value ) const override; /// /// @brief Decode Soft post package repair (soft PPR) @@ -581,7 +581,7 @@ class decoder_v1_0 : public decoder /// @note Page 21 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode soft_post_package_repair( uint8_t& o_value ) override; + virtual fapi2::ReturnCode soft_post_package_repair( uint8_t& o_value ) const override; /// /// @brief Decodes Secondary SDRAM signal loading @@ -591,7 +591,7 @@ class decoder_v1_0 : public decoder /// @note Page 22 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode sec_sdram_signal_loading( uint8_t& o_value ) override; + virtual fapi2::ReturnCode sec_sdram_signal_loading( uint8_t& o_value ) const override; /// /// @brief Decodes Secondary DRAM Density Ratio @@ -601,7 +601,7 @@ class decoder_v1_0 : public decoder /// @note Page 22 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode sec_dram_density_ratio( uint8_t& o_value ) override; + virtual fapi2::ReturnCode sec_dram_density_ratio( uint8_t& o_value ) const override; /// /// @brief Decodes Secondary SDRAM die count @@ -611,7 +611,7 @@ class decoder_v1_0 : public decoder /// @note Page 22 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode sec_sdram_die_count( uint8_t& o_value ) override; + virtual fapi2::ReturnCode sec_sdram_die_count( uint8_t& o_value ) const override; /// /// @brief Decodes Secondary SDRAM package type @@ -621,7 +621,7 @@ class decoder_v1_0 : public decoder /// @note Page 22 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode sec_sdram_package_type( uint8_t& o_value ) override; + virtual fapi2::ReturnCode sec_sdram_package_type( uint8_t& o_value ) const override; /// /// @brief Decode Module Nominal Voltage, VDD @@ -632,7 +632,7 @@ class decoder_v1_0 : public decoder /// @note Page 23 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode operable_nominal_voltage( uint8_t& o_value ) override; + virtual fapi2::ReturnCode operable_nominal_voltage( uint8_t& o_value ) const override; /// /// @brief Decode Module Nominal Voltage, VDD @@ -643,7 +643,7 @@ class decoder_v1_0 : public decoder /// @note Page 23 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode endurant_nominal_voltage( uint8_t& o_value ) override; + virtual fapi2::ReturnCode endurant_nominal_voltage( uint8_t& o_value ) const override; /// /// @brief Decodes SDRAM device width /// @param[out] o_value device width in bits @@ -653,7 +653,7 @@ class decoder_v1_0 : public decoder /// @note Page 23 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode device_width( uint8_t& o_value ) override; + virtual fapi2::ReturnCode device_width( uint8_t& o_value ) const override; /// /// @brief Decodes number of package ranks per DIMM @@ -664,7 +664,7 @@ class decoder_v1_0 : public decoder /// @note Page 23 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode num_package_ranks_per_dimm( uint8_t& o_value ) override; + virtual fapi2::ReturnCode num_package_ranks_per_dimm( uint8_t& o_value ) const override; /// /// @brief Decodes Rank Mix @@ -675,7 +675,7 @@ class decoder_v1_0 : public decoder /// @note Page 23 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode rank_mix( uint8_t& o_value ) override; + virtual fapi2::ReturnCode rank_mix( uint8_t& o_value ) const override; /// /// @brief Decodes primary bus width @@ -686,7 +686,7 @@ class decoder_v1_0 : public decoder /// @note Page 27 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode prim_bus_width( uint8_t& o_value ) override; + virtual fapi2::ReturnCode prim_bus_width( uint8_t& o_value ) const override; /// /// @brief Decodes bus width extension @@ -697,7 +697,7 @@ class decoder_v1_0 : public decoder /// @note Page 27 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode bus_width_extension( uint8_t& o_value ) override; + virtual fapi2::ReturnCode bus_width_extension( uint8_t& o_value ) const override; /// /// @brief Decode Module Thermal Sensor @@ -708,7 +708,7 @@ class decoder_v1_0 : public decoder /// @note Page 28 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode thermal_sensor( uint8_t& o_value ) override; + virtual fapi2::ReturnCode thermal_sensor( uint8_t& o_value ) const override; /// /// @brief Decode Extended Base Module Type @@ -719,7 +719,7 @@ class decoder_v1_0 : public decoder /// @note Page 28 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode extended_base_module_type( uint8_t& o_value ) override; + virtual fapi2::ReturnCode extended_base_module_type( uint8_t& o_value ) const override; /// /// @brief Decode Fine Timebase @@ -730,7 +730,7 @@ class decoder_v1_0 : public decoder /// @note Page 29 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode fine_timebase( int64_t& o_value ) override; + virtual fapi2::ReturnCode fine_timebase( int64_t& o_value ) const override; /// /// @brief Decode Medium Timebase @@ -741,7 +741,7 @@ class decoder_v1_0 : public decoder /// @note Page 29 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode medium_timebase( int64_t& o_value ) override; + virtual fapi2::ReturnCode medium_timebase( int64_t& o_value ) const override; /// /// @@ -757,7 +757,7 @@ class decoder_v1_0 : public decoder /// integer and the Fine Offset for tCKmin (SPD byte 125) /// used for correction to get the actual value. /// - virtual fapi2::ReturnCode min_tck( int64_t& o_value ) override; + virtual fapi2::ReturnCode min_tck( int64_t& o_value ) const override; /// /// @brief Decodes SDRAM Maximum Cycle Time in MTB @@ -772,7 +772,7 @@ class decoder_v1_0 : public decoder /// integer and the Fine Offset for tCKmax (SPD byte 124) /// used for correction to get the actual value. /// - virtual fapi2::ReturnCode max_tck( int64_t& o_value ) override; + virtual fapi2::ReturnCode max_tck( int64_t& o_value ) const override; /// /// @brief Decode CAS Latencies Supported @@ -783,7 +783,7 @@ class decoder_v1_0 : public decoder /// @note Page 33-34 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode supported_cas_latencies( uint64_t& o_value ) override; + virtual fapi2::ReturnCode supported_cas_latencies( uint64_t& o_value ) const override; /// /// @brief Decodes SDRAM Minimum CAS Latency Time in MTB @@ -798,7 +798,7 @@ class decoder_v1_0 : public decoder /// integer and the Fine Offset for tAAmin (SPD byte 123) /// used for correction to get the actual value. /// - virtual fapi2::ReturnCode min_taa( int64_t& o_value ) override; + virtual fapi2::ReturnCode min_taa( int64_t& o_value ) const override; /// /// @brief Decodes SDRAM Minimum RAS to CAS Delay Time in MTB @@ -813,7 +813,7 @@ class decoder_v1_0 : public decoder /// integer and the Fine Offset for tRCDmin (SPD byte 122) /// used for correction to get the actual value /// - virtual fapi2::ReturnCode min_trcd( int64_t& o_value ) override; + virtual fapi2::ReturnCode min_trcd( int64_t& o_value ) const override; /// /// @brief Decodes SDRAM Minimum Row Precharge Delay Time in MTB @@ -828,7 +828,7 @@ class decoder_v1_0 : public decoder /// integer and the Fine Offset for tRPmin (SPD byte 121) /// used for correction to get the actual value /// - virtual fapi2::ReturnCode min_trp( int64_t& o_value ) override; + virtual fapi2::ReturnCode min_trp( int64_t& o_value ) const override; /// /// @brief Decodes SDRAM Minimum Active to Precharge Delay Time in MTB @@ -839,7 +839,7 @@ class decoder_v1_0 : public decoder /// @note Page 38 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode min_tras( int64_t& o_value ) override; + virtual fapi2::ReturnCode min_tras( int64_t& o_value ) const override; /// /// @brief Decodes SDRAM Minimum Active to Active/Refresh Delay Time in MTB @@ -854,7 +854,7 @@ class decoder_v1_0 : public decoder /// integer and the Fine Offset for tRCmin (SPD byte 120) /// used for correction to get the actual value. /// - virtual fapi2::ReturnCode min_trc( int64_t& o_value ) override; + virtual fapi2::ReturnCode min_trc( int64_t& o_value ) const override; /// /// @brief Decodes SDRAM Minimum Refresh Recovery Delay Time 1 @@ -865,7 +865,7 @@ class decoder_v1_0 : public decoder /// @note Page 39-40 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode min_trfc1( int64_t& o_value ) override; + virtual fapi2::ReturnCode min_trfc1( int64_t& o_value ) const override; /// /// @brief Decodes SDRAM Minimum Refresh Recovery Delay Time 2 @@ -876,7 +876,7 @@ class decoder_v1_0 : public decoder /// @note Page 40 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode min_trfc2( int64_t& o_value ) override; + virtual fapi2::ReturnCode min_trfc2( int64_t& o_value ) const override; /// /// @brief Decodes SDRAM Minimum Refresh Recovery Delay Time 4 @@ -887,7 +887,7 @@ class decoder_v1_0 : public decoder /// @note Page 40 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode min_trfc4( int64_t& o_value ) override; + virtual fapi2::ReturnCode min_trfc4( int64_t& o_value ) const override; /// /// @brief Decodes SDRAM Minimum Four Activate Window Delay Time @@ -898,7 +898,7 @@ class decoder_v1_0 : public decoder /// @note Page 42 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode min_tfaw( int64_t& o_value ) override; + virtual fapi2::ReturnCode min_tfaw( int64_t& o_value ) const override; /// /// @brief Decodes Minimum Activate to Activate Delay Time - Different Bank Group @@ -913,7 +913,7 @@ class decoder_v1_0 : public decoder /// integer and the Fine Offset for tRRD_Smin (SPD byte 119) /// used for correction to get the actual value. /// - virtual fapi2::ReturnCode min_trrd_s( int64_t& o_value ) override; + virtual fapi2::ReturnCode min_trrd_s( int64_t& o_value ) const override; /// /// @brief Decodes Minimum Activate to Activate Delay Time - Same Bank Group @@ -928,7 +928,7 @@ class decoder_v1_0 : public decoder /// integer and the Fine Offset for tRRD_Lmin (SPD byte 118) /// used for correction to get the actual value. /// - virtual fapi2::ReturnCode min_trrd_l( int64_t& o_value ) override; + virtual fapi2::ReturnCode min_trrd_l( int64_t& o_value ) const override; /// /// @brief Decodes Minimum CAS to CAS Delay Time - Same Bank Group @@ -943,7 +943,7 @@ class decoder_v1_0 : public decoder /// integer and the Fine Offset for tCCD_Lmin (SPD byte 117) /// used for correction to get the actual value. /// - virtual fapi2::ReturnCode min_tccd_l( int64_t& o_value ) override; + virtual fapi2::ReturnCode min_tccd_l( int64_t& o_value ) const override; /// /// @brief Decodes Minimum Write Recovery Time @@ -954,7 +954,7 @@ class decoder_v1_0 : public decoder /// @note Page 40 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode min_twr( int64_t& o_value ) override; + virtual fapi2::ReturnCode min_twr( int64_t& o_value ) const override; /// /// @brief Decodes Minimum Write to Read Time - Different Bank Group @@ -965,7 +965,7 @@ class decoder_v1_0 : public decoder /// @note Page 40 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode min_twtr_s( int64_t& o_value ) override; + virtual fapi2::ReturnCode min_twtr_s( int64_t& o_value ) const override; /// /// @brief Decodes Minimum Write to Read Time - Same Bank Group @@ -976,7 +976,7 @@ class decoder_v1_0 : public decoder /// @note Page 46 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode min_twtr_l( int64_t& o_value ) override; + virtual fapi2::ReturnCode min_twtr_l( int64_t& o_value ) const override; /// /// @brief Decodes Fine Offset for Minimum CAS to CAS Delay Time - Same Bank Group @@ -987,7 +987,7 @@ class decoder_v1_0 : public decoder /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode fine_offset_min_tccd_l( int64_t& o_value ) override; + virtual fapi2::ReturnCode fine_offset_min_tccd_l( int64_t& o_value ) const override; /// /// @brief Decodes Fine Offset for Minimum Activate to Activate Delay Time - Same Bank Group @@ -998,7 +998,7 @@ class decoder_v1_0 : public decoder /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode fine_offset_min_trrd_l( int64_t& o_value ) override; + virtual fapi2::ReturnCode fine_offset_min_trrd_l( int64_t& o_value ) const override; /// /// @brief Decodes Fine Offset for Minimum Activate to Activate Delay Time - Different Bank Group @@ -1009,7 +1009,7 @@ class decoder_v1_0 : public decoder /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode fine_offset_min_trrd_s( int64_t& o_value ) override; + virtual fapi2::ReturnCode fine_offset_min_trrd_s( int64_t& o_value ) const override; /// /// @brief Decodes Fine Offset for Minimum Active to Active/Refresh Delay Time @@ -1020,7 +1020,7 @@ class decoder_v1_0 : public decoder /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode fine_offset_min_trc( int64_t& o_value ) override; + virtual fapi2::ReturnCode fine_offset_min_trc( int64_t& o_value ) const override; /// /// @brief Decodes Fine Offset for Minimum Row Precharge Delay Time @@ -1031,7 +1031,7 @@ class decoder_v1_0 : public decoder /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode fine_offset_min_trp( int64_t& o_value ) override; + virtual fapi2::ReturnCode fine_offset_min_trp( int64_t& o_value ) const override; /// /// @brief Decodes Fine Offset for SDRAM Minimum RAS to CAS Delay Time @@ -1042,7 +1042,7 @@ class decoder_v1_0 : public decoder /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode fine_offset_min_trcd( int64_t& o_value ) override; + virtual fapi2::ReturnCode fine_offset_min_trcd( int64_t& o_value ) const override; /// /// @brief Decodes Fine Offset for SDRAM Minimum CAS Latency Time @@ -1053,7 +1053,7 @@ class decoder_v1_0 : public decoder /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode fine_offset_min_taa( int64_t& o_value ) override; + virtual fapi2::ReturnCode fine_offset_min_taa( int64_t& o_value ) const override; /// /// @brief Decodes Fine Offset for SDRAM Maximum Cycle Time @@ -1064,7 +1064,7 @@ class decoder_v1_0 : public decoder /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode fine_offset_max_tck( int64_t& o_value ) override; + virtual fapi2::ReturnCode fine_offset_max_tck( int64_t& o_value ) const override; /// /// @brief Decodes Fine Offset for SDRAM Minimum Cycle Time @@ -1075,7 +1075,7 @@ class decoder_v1_0 : public decoder /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode fine_offset_min_tck( int64_t& o_value ) override; + virtual fapi2::ReturnCode fine_offset_min_tck( int64_t& o_value ) const override; /// /// @brief Decodes Cyclical Redundancy Code (CRC) for Base Configuration Section @@ -1086,7 +1086,7 @@ class decoder_v1_0 : public decoder /// @note Page 53 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode cyclical_redundancy_code( uint16_t& o_value ) override; + virtual fapi2::ReturnCode cyclical_redundancy_code( uint16_t& o_value ) const override; /// /// @brief Decodes module manufacturer ID code @@ -1097,7 +1097,7 @@ class decoder_v1_0 : public decoder /// @note DDR4 SPD Document Release 3 /// @note Page 4.1.2.12 - 54 /// - virtual fapi2::ReturnCode module_manufacturer_id_code( uint16_t& o_value ) override; + virtual fapi2::ReturnCode module_manufacturer_id_code( uint16_t& o_value ) const override; /// /// @brief Decodes Module Manufacturing Location @@ -1108,7 +1108,7 @@ class decoder_v1_0 : public decoder /// @note Page 55 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode module_manufacturing_location( uint8_t& o_value ) override; + virtual fapi2::ReturnCode module_manufacturing_location( uint8_t& o_value ) const override; /// /// @brief Decodesmodule manufacturing date /// @param[out] o_output the 2 byte date of manufacturing in BCD format @@ -1120,7 +1120,7 @@ class decoder_v1_0 : public decoder /// @note in Binary Coded Decimal (BCD) /// @note MSB = year, LSB = week /// - virtual fapi2::ReturnCode module_manufacturing_date( uint16_t& o_output ) override; + virtual fapi2::ReturnCode module_manufacturing_date( uint16_t& o_output ) const override; /// /// @brief Decodes module's unique serial number @@ -1131,7 +1131,7 @@ class decoder_v1_0 : public decoder /// @note DDR4 SPD Document Release 2 /// @note Page 4.1.2.12 - 54 /// - virtual fapi2::ReturnCode module_serial_number( uint32_t& o_output ) override; + virtual fapi2::ReturnCode module_serial_number( uint32_t& o_output ) const override; /// /// @brief Decodes Module Revision Code @@ -1142,7 +1142,7 @@ class decoder_v1_0 : public decoder /// @note Page 55 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode module_revision_code( uint8_t& o_value ) override; + virtual fapi2::ReturnCode module_revision_code( uint8_t& o_value ) const override; /// /// @brief Decodes DRAM Manufacturer ID code @@ -1153,7 +1153,7 @@ class decoder_v1_0 : public decoder /// @note DDR4 SPD Document Release 2 /// @note Page 4.1.2.12 - 54 /// - virtual fapi2::ReturnCode dram_manufacturer_id_code( uint16_t& o_output ) override; + virtual fapi2::ReturnCode dram_manufacturer_id_code( uint16_t& o_output ) const override; /// /// @brief Decodes DRAM Stepping /// @param[out] o_value uint8_t DRAM Stepping val @@ -1164,14 +1164,14 @@ class decoder_v1_0 : public decoder /// @note DDR4 SPD Document Release 3 /// @note also called die revision level /// - virtual fapi2::ReturnCode dram_stepping( uint8_t& o_value ) override; + virtual fapi2::ReturnCode dram_stepping( uint8_t& o_value ) const override; /// /// @brief Returns Logical ranks per DIMM /// @param[out] o_logical_ranks number of logical ranks /// @return fapi2::FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode logical_ranks_per_dimm( uint8_t& o_logical_rank_per_dimm ) override; + virtual fapi2::ReturnCode logical_ranks_per_dimm( uint8_t& o_logical_rank_per_dimm ) const override; };// decoder @@ -1188,7 +1188,7 @@ class decoder_v1_1 : public decoder_v1_0 /// @param[out] o_logical_ranks number of logical ranks /// @return fapi2::FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode sec_sdram_logical_ranks( uint8_t& o_logical_ranks ); + virtual fapi2::ReturnCode sec_sdram_logical_ranks( uint8_t& o_logical_ranks ) const; public: /// @@ -1226,7 +1226,7 @@ class decoder_v1_1 : public decoder_v1_0 /// @note Page 17 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode hybrid_media( uint8_t& o_value) override; + virtual fapi2::ReturnCode hybrid_media( uint8_t& o_value) const override; /// /// @brief Decodes hybrid field from SPD @@ -1237,7 +1237,7 @@ class decoder_v1_1 : public decoder_v1_0 /// @note Page 17 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode hybrid( uint8_t& o_value ) override; + virtual fapi2::ReturnCode hybrid( uint8_t& o_value ) const override; /// /// @brief Decodes SDRAM density from SPD @@ -1248,7 +1248,7 @@ class decoder_v1_1 : public decoder_v1_0 /// @note Page 18 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode sdram_density( uint8_t& o_value ) override; + virtual fapi2::ReturnCode sdram_density( uint8_t& o_value ) const override; /// /// @brief Decode Soft post package repair (soft PPR) @@ -1258,7 +1258,7 @@ class decoder_v1_1 : public decoder_v1_0 /// @note Page 21 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode soft_post_package_repair( uint8_t& o_value ) override; + virtual fapi2::ReturnCode soft_post_package_repair( uint8_t& o_value ) const override; /// /// @brief Decodes Secondary SDRAM signal loading @@ -1268,7 +1268,7 @@ class decoder_v1_1 : public decoder_v1_0 /// @note Page 22 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode sec_sdram_signal_loading( uint8_t& o_value ) override; + virtual fapi2::ReturnCode sec_sdram_signal_loading( uint8_t& o_value ) const override; /// /// @brief Decodes Secondary DRAM Density Ratio @@ -1278,7 +1278,7 @@ class decoder_v1_1 : public decoder_v1_0 /// @note Page 22 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode sec_dram_density_ratio( uint8_t& o_value ) override; + virtual fapi2::ReturnCode sec_dram_density_ratio( uint8_t& o_value ) const override; /// /// @brief Decodes Secondary SDRAM die count @@ -1288,7 +1288,7 @@ class decoder_v1_1 : public decoder_v1_0 /// @note Page 22 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode sec_sdram_die_count( uint8_t& o_value ) override; + virtual fapi2::ReturnCode sec_sdram_die_count( uint8_t& o_value ) const override; /// /// @brief Decodes Secondary SDRAM package type @@ -1298,7 +1298,7 @@ class decoder_v1_1 : public decoder_v1_0 /// @note Page 22 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode sec_sdram_package_type( uint8_t& o_value ) override; + virtual fapi2::ReturnCode sec_sdram_package_type( uint8_t& o_value ) const override; /// /// @brief Decodes number of package ranks per DIMM @@ -1309,7 +1309,7 @@ class decoder_v1_1 : public decoder_v1_0 /// @note Page 23 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode num_package_ranks_per_dimm( uint8_t& o_value ) override; + virtual fapi2::ReturnCode num_package_ranks_per_dimm( uint8_t& o_value ) const override; /// /// @brief Decodes Rank Mix @@ -1320,7 +1320,7 @@ class decoder_v1_1 : public decoder_v1_0 /// @note Page 23 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode rank_mix( uint8_t& o_value ) override; + virtual fapi2::ReturnCode rank_mix( uint8_t& o_value ) const override; /// /// @brief Decode CAS Latencies Supported @@ -1331,7 +1331,7 @@ class decoder_v1_1 : public decoder_v1_0 /// @note Page 33-34 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode supported_cas_latencies( uint64_t& o_value) override; + virtual fapi2::ReturnCode supported_cas_latencies( uint64_t& o_value) const override; /// /// @brief Decodes Minimum Write Recovery Time @@ -1342,7 +1342,7 @@ class decoder_v1_1 : public decoder_v1_0 /// @note Page 40 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode min_twr( int64_t& o_value ) override; + virtual fapi2::ReturnCode min_twr( int64_t& o_value ) const override; /// /// @brief Decodes Minimum Write to Read Time - Different Bank Group @@ -1353,7 +1353,7 @@ class decoder_v1_1 : public decoder_v1_0 /// @note Page 40 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode min_twtr_s( int64_t& o_value ) override; + virtual fapi2::ReturnCode min_twtr_s( int64_t& o_value ) const override; /// /// @brief Decodes Minimum Write to Read Time - Same Bank Group @@ -1364,14 +1364,14 @@ class decoder_v1_1 : public decoder_v1_0 /// @note Page 46 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode min_twtr_l( int64_t& o_value ) override; + virtual fapi2::ReturnCode min_twtr_l( int64_t& o_value ) const override; /// /// @brief Returns Logical ranks per DIMM /// @param[out] o_logical_ranks number of logical ranks /// @return fapi2::FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode logical_ranks_per_dimm( uint8_t& o_logical_rank_per_dimm ) override; + virtual fapi2::ReturnCode logical_ranks_per_dimm( uint8_t& o_logical_rank_per_dimm ) const override; };// spd_decoder_v1_1 diff --git a/src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4_v1_0.C b/src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4_v1_0.C index 38ac4afe9..baca956f8 100644 --- a/src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4_v1_0.C +++ b/src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4_v1_0.C @@ -85,7 +85,7 @@ decoder_v1_0::decoder_v1_0(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_targe /// @note Page 14 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::number_of_used_bytes( uint16_t& o_value ) +fapi2::ReturnCode decoder_v1_0::number_of_used_bytes( uint16_t& o_value ) const { // ========================================================= // Byte 0 maps @@ -133,7 +133,7 @@ fapi_try_exit: /// @note Page 14 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::number_of_total_bytes( uint16_t& o_value ) +fapi2::ReturnCode decoder_v1_0::number_of_total_bytes( uint16_t& o_value ) const { // ========================================================= @@ -180,7 +180,7 @@ fapi_try_exit: /// @note Page 17 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::hybrid_media( uint8_t& o_value) +fapi2::ReturnCode decoder_v1_0::hybrid_media( uint8_t& o_value) const { // For General Section rev 1.0 of the SPD, // Decodes SPD Byte 3 (bits 4~6) were reserved @@ -200,7 +200,7 @@ fapi2::ReturnCode decoder_v1_0::hybrid_media( uint8_t& o_value) /// @note Page 17 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::hybrid( uint8_t& o_value) +fapi2::ReturnCode decoder_v1_0::hybrid( uint8_t& o_value) const { // For General Section rev 1.0 of the SPD, // Decodes SPD Byte 3 (bit 7) were reserved @@ -219,7 +219,7 @@ fapi2::ReturnCode decoder_v1_0::hybrid( uint8_t& o_value) /// @note Page 18 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::sdram_density( uint8_t& o_value) +fapi2::ReturnCode decoder_v1_0::sdram_density( uint8_t& o_value) const { // ========================================================= // Byte 4 maps @@ -269,7 +269,7 @@ fapi_try_exit: /// @note Page 18 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::bank_bits( uint8_t& o_value) +fapi2::ReturnCode decoder_v1_0::bank_bits( uint8_t& o_value) const { // ========================================================= @@ -316,7 +316,7 @@ fapi_try_exit: /// @note Page 18 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::bank_group_bits( uint8_t& o_value) +fapi2::ReturnCode decoder_v1_0::bank_group_bits( uint8_t& o_value) const { // ========================================================= // Byte 4 maps @@ -363,7 +363,7 @@ fapi_try_exit: /// @note Page 18 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::column_address_bits( uint8_t& o_value) +fapi2::ReturnCode decoder_v1_0::column_address_bits( uint8_t& o_value) const { // ========================================================= // Byte 5 maps @@ -411,7 +411,7 @@ fapi_try_exit: /// @note Page 18 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::row_address_bits( uint8_t& o_value) +fapi2::ReturnCode decoder_v1_0::row_address_bits( uint8_t& o_value) const { // ========================================================= // Byte 5 maps @@ -463,7 +463,7 @@ fapi_try_exit: /// @note Page 19 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::prim_sdram_signal_loading( uint8_t& o_value) +fapi2::ReturnCode decoder_v1_0::prim_sdram_signal_loading( uint8_t& o_value) const { // ========================================================= // Byte 6 maps @@ -510,7 +510,7 @@ fapi_try_exit: /// @note Page 19 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::prim_sdram_die_count( uint8_t& o_value) +fapi2::ReturnCode decoder_v1_0::prim_sdram_die_count( uint8_t& o_value) const { // ========================================================= // Byte 6 maps @@ -562,7 +562,7 @@ fapi_try_exit: /// @note Page 19 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::prim_sdram_package_type( uint8_t& o_value) +fapi2::ReturnCode decoder_v1_0::prim_sdram_package_type( uint8_t& o_value) const { // ========================================================= // Byte 6 maps @@ -609,7 +609,7 @@ fapi_try_exit: /// @note Page 20 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::maximum_activate_count( uint32_t& o_value ) +fapi2::ReturnCode decoder_v1_0::maximum_activate_count( uint32_t& o_value ) const { // ========================================================= // Byte 7 maps @@ -661,7 +661,7 @@ fapi_try_exit: /// @note Page 20 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::maximum_activate_window_multiplier( uint32_t& o_value ) +fapi2::ReturnCode decoder_v1_0::maximum_activate_window_multiplier( uint32_t& o_value ) const { // ========================================================= // Byte 7 maps @@ -709,7 +709,7 @@ fapi_try_exit: /// @note Page 21 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::post_package_repair( uint8_t& o_value) +fapi2::ReturnCode decoder_v1_0::post_package_repair( uint8_t& o_value) const { // ========================================================= // Byte 9 maps @@ -755,7 +755,7 @@ fapi_try_exit: /// @note Page 22 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::sec_sdram_signal_loading( uint8_t& o_value) +fapi2::ReturnCode decoder_v1_0::sec_sdram_signal_loading( uint8_t& o_value) const { // For General Section rev 1.0 of the SPD, // SPD Byte 10 (bits 1~0) were reserved @@ -775,7 +775,7 @@ fapi2::ReturnCode decoder_v1_0::sec_sdram_signal_loading( uint8_t& o_value) /// @note Page 21 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::soft_post_package_repair( uint8_t& o_value) +fapi2::ReturnCode decoder_v1_0::soft_post_package_repair( uint8_t& o_value) const { // For General Section rev 1.0 of the SPD, // SPD Byte 9 (bit 5) was reserved @@ -794,7 +794,7 @@ fapi2::ReturnCode decoder_v1_0::soft_post_package_repair( uint8_t& o_value) /// @note Page 22 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::sec_dram_density_ratio( uint8_t& o_value) +fapi2::ReturnCode decoder_v1_0::sec_dram_density_ratio( uint8_t& o_value) const { // For General Section rev 1.0 of the SPD, // SPD Byte 10 (bits 3~2) were reserved @@ -814,7 +814,7 @@ fapi2::ReturnCode decoder_v1_0::sec_dram_density_ratio( uint8_t& o_value) /// @note Page 22 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::sec_sdram_die_count( uint8_t& o_value) +fapi2::ReturnCode decoder_v1_0::sec_sdram_die_count( uint8_t& o_value) const { // For General Section rev 1.0 of the SPD, // SPD Byte 10 (bits 6~4) were reserved @@ -834,7 +834,7 @@ fapi2::ReturnCode decoder_v1_0::sec_sdram_die_count( uint8_t& o_value) /// @note Page 22 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::sec_sdram_package_type( uint8_t& o_value) +fapi2::ReturnCode decoder_v1_0::sec_sdram_package_type( uint8_t& o_value) const { // For General Section rev 1.0 of the SPD, // SPD Byte 10 (bit 7) was reserved @@ -854,7 +854,7 @@ fapi2::ReturnCode decoder_v1_0::sec_sdram_package_type( uint8_t& o_value) /// @note Page 23 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::operable_nominal_voltage( uint8_t& o_value) +fapi2::ReturnCode decoder_v1_0::operable_nominal_voltage( uint8_t& o_value) const { // ========================================================= // Byte 11 maps @@ -900,7 +900,7 @@ fapi_try_exit: /// @note Page 23 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::endurant_nominal_voltage( uint8_t& o_value) +fapi2::ReturnCode decoder_v1_0::endurant_nominal_voltage( uint8_t& o_value) const { // ========================================================= // Byte 11 maps @@ -947,7 +947,7 @@ fapi_try_exit: /// @note Page 23 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::device_width( uint8_t& o_value) +fapi2::ReturnCode decoder_v1_0::device_width( uint8_t& o_value) const { // ========================================================= // Byte 12 maps @@ -997,7 +997,7 @@ fapi_try_exit: /// @note Page 23 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::num_package_ranks_per_dimm( uint8_t& o_value) +fapi2::ReturnCode decoder_v1_0::num_package_ranks_per_dimm( uint8_t& o_value) const { // ========================================================= // Byte 12 maps @@ -1046,7 +1046,7 @@ fapi_try_exit: /// @note Page 23 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::rank_mix( uint8_t& o_value) +fapi2::ReturnCode decoder_v1_0::rank_mix( uint8_t& o_value) const { // For General Section rev 1.0 of the SPD, // Decodes SPD Byte 3 (bits 4~6) were reserved @@ -1066,7 +1066,7 @@ fapi2::ReturnCode decoder_v1_0::rank_mix( uint8_t& o_value) /// @note Page 27 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::prim_bus_width( uint8_t& o_value) +fapi2::ReturnCode decoder_v1_0::prim_bus_width( uint8_t& o_value) const { // ========================================================= // Byte 13 maps @@ -1115,7 +1115,7 @@ fapi_try_exit: /// @note Page 28 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::bus_width_extension( uint8_t& o_value) +fapi2::ReturnCode decoder_v1_0::bus_width_extension( uint8_t& o_value) const { // ========================================================= // Byte 13 maps @@ -1162,7 +1162,7 @@ fapi_try_exit: /// @note Page 28 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::thermal_sensor( uint8_t& o_value) +fapi2::ReturnCode decoder_v1_0::thermal_sensor( uint8_t& o_value) const { // Extracting desired bits const uint8_t l_field_bits = extract_spd_field< THERM_SENSOR >(iv_target, iv_spd_data); @@ -1196,7 +1196,7 @@ fapi_try_exit: /// @note Page 28 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::extended_base_module_type( uint8_t& o_value) +fapi2::ReturnCode decoder_v1_0::extended_base_module_type( uint8_t& o_value) const { // Extracting desired bits const uint8_t l_field_bits = extract_spd_field< EXTENDED_MODULE_TYPE >(iv_target, iv_spd_data); @@ -1232,7 +1232,7 @@ fapi_try_exit: /// @note Page 29 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::fine_timebase( int64_t& o_value) +fapi2::ReturnCode decoder_v1_0::fine_timebase( int64_t& o_value) const { // ========================================================= // Byte 17 maps @@ -1279,7 +1279,7 @@ fapi_try_exit: /// @note Page 29 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::medium_timebase( int64_t& o_value) +fapi2::ReturnCode decoder_v1_0::medium_timebase( int64_t& o_value) const { // ========================================================= // Byte 17 maps @@ -1331,7 +1331,7 @@ fapi_try_exit: /// integer and the Fine Offset for tCKmin (SPD byte 125) /// used for correction to get the actual value. /// -fapi2::ReturnCode decoder_v1_0::min_tck( int64_t& o_value ) +fapi2::ReturnCode decoder_v1_0::min_tck( int64_t& o_value ) const { // Explicit conversion constexpr size_t BYTE_INDEX = 18; @@ -1378,7 +1378,7 @@ fapi_try_exit: /// integer and the Fine Offset for tCKmax (SPD byte 124) /// used for correction to get the actual value. /// -fapi2::ReturnCode decoder_v1_0::max_tck( int64_t& o_value ) +fapi2::ReturnCode decoder_v1_0::max_tck( int64_t& o_value ) const { // Explicit conversion constexpr size_t BYTE_INDEX = 19; @@ -1422,7 +1422,7 @@ fapi_try_exit: /// @note Page 33-34 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::supported_cas_latencies( uint64_t& o_value ) +fapi2::ReturnCode decoder_v1_0::supported_cas_latencies( uint64_t& o_value ) const { // Trace print in the front assists w/ debug constexpr size_t FIRST_BYTE = 20; @@ -1499,7 +1499,7 @@ fapi_try_exit: /// integer and the Fine Offset for tAAmin (SPD byte 123) /// used for correction to get the actual value. /// -fapi2::ReturnCode decoder_v1_0::min_taa( int64_t& o_value ) +fapi2::ReturnCode decoder_v1_0::min_taa( int64_t& o_value ) const { // Explicit conversion constexpr size_t BYTE_INDEX = 24; @@ -1546,7 +1546,7 @@ fapi_try_exit: /// integer and the Fine Offset for tRCDmin (SPD byte 122) /// used for correction to get the actual value /// -fapi2::ReturnCode decoder_v1_0::min_trcd( int64_t& o_value ) +fapi2::ReturnCode decoder_v1_0::min_trcd( int64_t& o_value ) const { // Explicit conversion constexpr size_t BYTE_INDEX = 25; @@ -1593,7 +1593,7 @@ fapi_try_exit: /// integer and the Fine Offset for tRPmin (SPD byte 121) /// used for correction to get the actual value /// -fapi2::ReturnCode decoder_v1_0::min_trp( int64_t& o_value ) +fapi2::ReturnCode decoder_v1_0::min_trp( int64_t& o_value ) const { // Explicit conversion constexpr size_t BYTE_INDEX = 26; @@ -1637,7 +1637,7 @@ fapi_try_exit: /// @note Page 38 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::min_tras( int64_t& o_value) +fapi2::ReturnCode decoder_v1_0::min_tras( int64_t& o_value) const { uint8_t tRASmin_MSN = extract_spd_field< TRASMIN_MSN >(iv_target, iv_spd_data); FAPI_INF("MSN Field Bits value: %lu", tRASmin_MSN); @@ -1700,7 +1700,7 @@ fapi_try_exit: /// integer and the Fine Offset for tRCmin (SPD byte 120) /// used for correction to get the actual value. /// -fapi2::ReturnCode decoder_v1_0::min_trc( int64_t& o_value) +fapi2::ReturnCode decoder_v1_0::min_trc( int64_t& o_value) const { uint8_t tRCmin_MSN = extract_spd_field< TRCMIN_MSN >(iv_target, iv_spd_data); FAPI_INF("MSN Field Bits value: %lu", tRCmin_MSN); @@ -1758,7 +1758,7 @@ fapi_try_exit: /// @note Page 39-40 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::min_trfc1( int64_t& o_value) +fapi2::ReturnCode decoder_v1_0::min_trfc1( int64_t& o_value) const { uint8_t tRFC1min_MSB = extract_spd_field< TRFC1MIN_MSB >(iv_target, iv_spd_data); FAPI_INF("MSB Field Bits value: %lu", tRFC1min_MSB); @@ -1816,7 +1816,7 @@ fapi_try_exit: /// @note Page 40 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::min_trfc2( int64_t& o_value) +fapi2::ReturnCode decoder_v1_0::min_trfc2( int64_t& o_value) const { uint8_t tRFC2min_MSB = extract_spd_field< TRFC2MIN_MSB >(iv_target, iv_spd_data); FAPI_INF("MSB Field Bits value: %lu", tRFC2min_MSB); @@ -1874,7 +1874,7 @@ fapi_try_exit: /// @note Page 40 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::min_trfc4( int64_t& o_value) +fapi2::ReturnCode decoder_v1_0::min_trfc4( int64_t& o_value) const { uint8_t tRFC4min_MSB = extract_spd_field< TRFC4MIN_MSB >(iv_target, iv_spd_data); FAPI_INF("MSB Field Bits value: %lu", tRFC4min_MSB); @@ -1932,7 +1932,7 @@ fapi_try_exit: /// @note Page 42 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::min_tfaw( int64_t& o_value) +fapi2::ReturnCode decoder_v1_0::min_tfaw( int64_t& o_value) const { uint8_t tFAWmin_MSN = extract_spd_field< TFAWMIN_MSN >(iv_target, iv_spd_data); FAPI_INF("MSN Field Bits value: %lu", tFAWmin_MSN); @@ -1994,7 +1994,7 @@ fapi_try_exit: /// integer and the Fine Offset for tRRD_Smin (SPD byte 119) /// used for correction to get the actual value. /// -fapi2::ReturnCode decoder_v1_0::min_trrd_s( int64_t& o_value) +fapi2::ReturnCode decoder_v1_0::min_trrd_s( int64_t& o_value) const { // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 38; @@ -2043,7 +2043,7 @@ fapi_try_exit: /// integer and the Fine Offset for tRRD_Lmin (SPD byte 118) /// used for correction to get the actual value. /// -fapi2::ReturnCode decoder_v1_0::min_trrd_l( int64_t& o_value) +fapi2::ReturnCode decoder_v1_0::min_trrd_l( int64_t& o_value) const { // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 39; @@ -2092,7 +2092,7 @@ fapi_try_exit: /// integer and the Fine Offset for tCCD_Lmin (SPD byte 117) /// used for correction to get the actual value. /// -fapi2::ReturnCode decoder_v1_0::min_tccd_l( int64_t& o_value) +fapi2::ReturnCode decoder_v1_0::min_tccd_l( int64_t& o_value) const { // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 40; @@ -2137,7 +2137,7 @@ fapi_try_exit: /// @note Page 40 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::min_twr( int64_t& o_value) +fapi2::ReturnCode decoder_v1_0::min_twr( int64_t& o_value) const { // For General Section rev 1.0 of the SPD, // SPD Byte 41 (bits 3~0) & Byte 42 (bits 7~0) were reserved @@ -2159,7 +2159,7 @@ fapi2::ReturnCode decoder_v1_0::min_twr( int64_t& o_value) /// @note Page 40 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::min_twtr_s( int64_t& o_value) +fapi2::ReturnCode decoder_v1_0::min_twtr_s( int64_t& o_value) const { // For General Section rev 1.0 of the SPD, // SPD Byte 43 (bits 3~0) & Byte 44 (bits 7~0) were reserved @@ -2180,7 +2180,7 @@ fapi2::ReturnCode decoder_v1_0::min_twtr_s( int64_t& o_value) /// @note Page 46 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::min_twtr_l( int64_t& o_value) +fapi2::ReturnCode decoder_v1_0::min_twtr_l( int64_t& o_value) const { // For General Section rev 1.0 of the SPD, // SPD Byte 43 (bits 7~4) & Byte 45 (bits 7~0) were reserved @@ -2202,7 +2202,7 @@ fapi2::ReturnCode decoder_v1_0::min_twtr_l( int64_t& o_value) /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::fine_offset_min_tccd_l( int64_t& o_value) +fapi2::ReturnCode decoder_v1_0::fine_offset_min_tccd_l( int64_t& o_value) const { // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 117; @@ -2248,7 +2248,7 @@ fapi_try_exit: /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::fine_offset_min_trrd_l( int64_t& o_value) +fapi2::ReturnCode decoder_v1_0::fine_offset_min_trrd_l( int64_t& o_value) const { // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 118; @@ -2294,7 +2294,7 @@ fapi_try_exit: /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::fine_offset_min_trrd_s( int64_t& o_value) +fapi2::ReturnCode decoder_v1_0::fine_offset_min_trrd_s( int64_t& o_value) const { // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 119; @@ -2340,7 +2340,7 @@ fapi_try_exit: /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::fine_offset_min_trc( int64_t& o_value) +fapi2::ReturnCode decoder_v1_0::fine_offset_min_trc( int64_t& o_value) const { // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 120; @@ -2386,7 +2386,7 @@ fapi_try_exit: /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::fine_offset_min_trp( int64_t& o_value) +fapi2::ReturnCode decoder_v1_0::fine_offset_min_trp( int64_t& o_value) const { // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 121; @@ -2431,7 +2431,7 @@ fapi_try_exit: /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::fine_offset_min_trcd( int64_t& o_value) +fapi2::ReturnCode decoder_v1_0::fine_offset_min_trcd( int64_t& o_value) const { // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 122; @@ -2477,7 +2477,7 @@ fapi_try_exit: /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::fine_offset_min_taa( int64_t& o_value ) +fapi2::ReturnCode decoder_v1_0::fine_offset_min_taa( int64_t& o_value ) const { // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 123; @@ -2523,7 +2523,7 @@ fapi_try_exit: /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::fine_offset_max_tck( int64_t& o_value ) +fapi2::ReturnCode decoder_v1_0::fine_offset_max_tck( int64_t& o_value ) const { // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 124; @@ -2570,7 +2570,7 @@ fapi_try_exit: /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::fine_offset_min_tck( int64_t& o_value ) +fapi2::ReturnCode decoder_v1_0::fine_offset_min_tck( int64_t& o_value ) const { // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 125; @@ -2617,7 +2617,7 @@ fapi_try_exit: /// @note Page 53 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::cyclical_redundancy_code( uint16_t& o_value ) +fapi2::ReturnCode decoder_v1_0::cyclical_redundancy_code( uint16_t& o_value ) const { uint8_t crc_MSB = extract_spd_field< CRC_MSB >(iv_target, iv_spd_data); FAPI_INF("MSB Field Bits value: %lu", crc_MSB); @@ -2655,7 +2655,7 @@ fapi2::ReturnCode decoder_v1_0::cyclical_redundancy_code( uint16_t& o_value ) /// @note DDR4 SPD Document Release 3 /// @note Page 4.1.2.12 - 54 /// -fapi2::ReturnCode decoder_v1_0::module_manufacturer_id_code( uint16_t& o_value ) +fapi2::ReturnCode decoder_v1_0::module_manufacturer_id_code( uint16_t& o_value ) const { constexpr size_t BYTE_INDEX_MSB = 320; @@ -2692,7 +2692,7 @@ fapi2::ReturnCode decoder_v1_0::module_manufacturer_id_code( uint16_t& o_value ) /// @note Page 55 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::module_manufacturing_location( uint8_t& o_value) +fapi2::ReturnCode decoder_v1_0::module_manufacturing_location( uint8_t& o_value) const { // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 322; @@ -2722,7 +2722,7 @@ fapi2::ReturnCode decoder_v1_0::module_manufacturing_location( uint8_t& o_value) /// @note in Binary Coded Decimal (BCD) /// @note MSB = year, LSB = week /// -fapi2::ReturnCode decoder_v1_0::module_manufacturing_date( uint16_t& o_value ) +fapi2::ReturnCode decoder_v1_0::module_manufacturing_date( uint16_t& o_value ) const { constexpr size_t BYTE_INDEX_MSB = 323; @@ -2761,7 +2761,7 @@ fapi2::ReturnCode decoder_v1_0::module_manufacturing_date( uint16_t& o_value ) /// @note Page 4.1.2.12 - 54 /// @note in Binary Coded Decimal (BCD) /// -fapi2::ReturnCode decoder_v1_0::module_serial_number( uint32_t& o_value ) +fapi2::ReturnCode decoder_v1_0::module_serial_number( uint32_t& o_value ) const { constexpr size_t BYTE_INDEX_0 = 325; uint8_t sn_byte_0 = iv_spd_data[BYTE_INDEX_0]; @@ -2810,7 +2810,7 @@ fapi2::ReturnCode decoder_v1_0::module_serial_number( uint32_t& o_value ) /// @note Page 55 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_0::module_revision_code( uint8_t& o_value) +fapi2::ReturnCode decoder_v1_0::module_revision_code( uint8_t& o_value) const { // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 349; @@ -2838,7 +2838,7 @@ fapi2::ReturnCode decoder_v1_0::module_revision_code( uint8_t& o_value) /// @note DDR4 SPD Document Release 2 /// @note Page 4.1.2.12 - 54 /// -fapi2::ReturnCode decoder_v1_0::dram_manufacturer_id_code( uint16_t& o_value ) +fapi2::ReturnCode decoder_v1_0::dram_manufacturer_id_code( uint16_t& o_value ) const { constexpr size_t BYTE_INDEX_MSB = 350; uint8_t mfgid_MSB = iv_spd_data[BYTE_INDEX_MSB]; @@ -2875,7 +2875,7 @@ fapi2::ReturnCode decoder_v1_0::dram_manufacturer_id_code( uint16_t& o_value ) /// @note DDR4 SPD Document Release 3 /// @note also called die revision level /// -fapi2::ReturnCode decoder_v1_0::dram_stepping( uint8_t& o_value) +fapi2::ReturnCode decoder_v1_0::dram_stepping( uint8_t& o_value) const { // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 352; @@ -2898,7 +2898,7 @@ fapi2::ReturnCode decoder_v1_0::dram_stepping( uint8_t& o_value) /// @param[out] o_logical_ranks number of logical ranks /// @return fapi2::FAPI2_RC_SUCCESS if okay /// -fapi2::ReturnCode decoder_v1_0::prim_sdram_logical_ranks( uint8_t& o_logical_ranks ) +fapi2::ReturnCode decoder_v1_0::prim_sdram_logical_ranks( uint8_t& o_logical_ranks ) const { uint8_t l_signal_loading = 0; uint8_t l_ranks_per_dimm = 0; @@ -2932,7 +2932,7 @@ fapi_try_exit: /// @param[out] o_logical_ranks number of logical ranks /// @return fapi2::FAPI2_RC_SUCCESS if okay /// -fapi2::ReturnCode decoder_v1_0::logical_ranks_per_dimm( uint8_t& o_logical_rank_per_dimm ) +fapi2::ReturnCode decoder_v1_0::logical_ranks_per_dimm( uint8_t& o_logical_rank_per_dimm ) const { FAPI_TRY( prim_sdram_logical_ranks(o_logical_rank_per_dimm) ); diff --git a/src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4_v1_1.C b/src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4_v1_1.C index 9845a5b46..19b685261 100644 --- a/src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4_v1_1.C +++ b/src/import/generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4_v1_1.C @@ -79,7 +79,7 @@ decoder_v1_1::decoder_v1_1(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_targe /// @note Page 18 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_1::sdram_density( uint8_t& o_value ) +fapi2::ReturnCode decoder_v1_1::sdram_density( uint8_t& o_value ) const { // ========================================================= // Byte 4 maps @@ -132,7 +132,7 @@ fapi_try_exit: /// @note Page 17 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_1::hybrid_media( uint8_t& o_value ) +fapi2::ReturnCode decoder_v1_1::hybrid_media( uint8_t& o_value ) const { // ========================================================= // Byte 3 maps @@ -178,7 +178,7 @@ fapi_try_exit: /// @note Page 17 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_1::hybrid( uint8_t& o_value ) +fapi2::ReturnCode decoder_v1_1::hybrid( uint8_t& o_value ) const { // ========================================================= // Byte 3 maps @@ -224,7 +224,7 @@ fapi_try_exit: /// @note Page 22 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_1::sec_sdram_signal_loading( uint8_t& o_value ) +fapi2::ReturnCode decoder_v1_1::sec_sdram_signal_loading( uint8_t& o_value ) const { // ========================================================= // Byte 10 maps @@ -271,7 +271,7 @@ fapi_try_exit: /// @note Page 21 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_1::soft_post_package_repair( uint8_t& o_value ) +fapi2::ReturnCode decoder_v1_1::soft_post_package_repair( uint8_t& o_value ) const { // ========================================================= // Byte 9 maps @@ -317,7 +317,7 @@ fapi_try_exit: /// @note Page 22 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_1::sec_dram_density_ratio( uint8_t& o_value ) +fapi2::ReturnCode decoder_v1_1::sec_dram_density_ratio( uint8_t& o_value ) const { // Extracting desired bits const uint8_t l_field_bits = extract_spd_field< SEC_DENSITY_RATIO >(iv_target, iv_spd_data); @@ -350,7 +350,7 @@ fapi_try_exit: /// @note Page 22 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_1::sec_sdram_die_count( uint8_t& o_value ) +fapi2::ReturnCode decoder_v1_1::sec_sdram_die_count( uint8_t& o_value ) const { // ========================================================= // Byte 10 maps @@ -403,7 +403,7 @@ fapi_try_exit: /// @note Page 22 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_1::sec_sdram_package_type( uint8_t& o_value ) +fapi2::ReturnCode decoder_v1_1::sec_sdram_package_type( uint8_t& o_value ) const { // ========================================================= // Byte 10 maps @@ -450,7 +450,7 @@ fapi_try_exit: /// @note Page 23 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_1::num_package_ranks_per_dimm( uint8_t& o_value ) +fapi2::ReturnCode decoder_v1_1::num_package_ranks_per_dimm( uint8_t& o_value ) const { // ========================================================= // Byte 12 maps @@ -502,7 +502,7 @@ fapi_try_exit: /// @note Page 23 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_1::rank_mix( uint8_t& o_value ) +fapi2::ReturnCode decoder_v1_1::rank_mix( uint8_t& o_value ) const { // Extracting desired bits const uint8_t l_field_bits = extract_spd_field< RANK_MIX >(iv_target, iv_spd_data); @@ -537,7 +537,7 @@ fapi_try_exit: /// @note Page 33-34 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_1::supported_cas_latencies( uint64_t& o_value ) +fapi2::ReturnCode decoder_v1_1::supported_cas_latencies( uint64_t& o_value ) const { // Trace print in the front assists w/ debug constexpr size_t FIRST_BYTE = 20; @@ -610,7 +610,7 @@ fapi_try_exit: /// @note Page 40 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_1::min_twr( int64_t& o_value ) +fapi2::ReturnCode decoder_v1_1::min_twr( int64_t& o_value ) const { uint8_t tWRmin_MSN = extract_spd_field< TWRMIN_MSN >(iv_target, iv_spd_data); FAPI_INF("MSN Field Bits value: %lu", tWRmin_MSN); @@ -671,7 +671,7 @@ fapi_try_exit: /// @note Page 40 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_1::min_twtr_s( int64_t& o_value ) +fapi2::ReturnCode decoder_v1_1::min_twtr_s( int64_t& o_value ) const { uint8_t tWTR_Smin_MSN = extract_spd_field< TWTRMIN_S_MSN >(iv_target, iv_spd_data); FAPI_INF("MSN Field Bits value: %lu", tWTR_Smin_MSN); @@ -732,7 +732,7 @@ fapi_try_exit: /// @note Page 46 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder_v1_1::min_twtr_l( int64_t& o_value ) +fapi2::ReturnCode decoder_v1_1::min_twtr_l( int64_t& o_value ) const { // Extracting desired bits uint8_t tWTR_Lmin_MSN = extract_spd_field< TWTRMIN_L_MSN >(iv_target, iv_spd_data); @@ -789,7 +789,7 @@ fapi_try_exit: /// @param[out] o_logical_ranks number of logical ranks /// @return fapi2::FAPI2_RC_SUCCESS if okay /// -fapi2::ReturnCode decoder_v1_1::sec_sdram_logical_ranks( uint8_t& o_logical_ranks ) +fapi2::ReturnCode decoder_v1_1::sec_sdram_logical_ranks( uint8_t& o_logical_ranks ) const { uint8_t l_signal_loading = 0; uint8_t l_ranks_per_dimm = 0; @@ -822,7 +822,7 @@ fapi_try_exit: /// @param[out] o_logical_ranks number of logical ranks /// @return fapi2::FAPI2_RC_SUCCESS if okay /// -fapi2::ReturnCode decoder_v1_1::logical_ranks_per_dimm( uint8_t& o_logical_rank_per_dimm ) +fapi2::ReturnCode decoder_v1_1::logical_ranks_per_dimm( uint8_t& o_logical_rank_per_dimm ) const { uint8_t l_rank_mix = 0; diff --git a/src/import/generic/memory/lib/spd/common/dimm_module_decoder.H b/src/import/generic/memory/lib/spd/common/dimm_module_decoder.H index 67faa47a0..318bd6b86 100644 --- a/src/import/generic/memory/lib/spd/common/dimm_module_decoder.H +++ b/src/import/generic/memory/lib/spd/common/dimm_module_decoder.H @@ -69,7 +69,7 @@ class dimm_module_decoder /// @param[out] o_output height range encoding from SPD /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode max_module_nominal_height(uint8_t& o_output) + virtual fapi2::ReturnCode max_module_nominal_height(uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -80,7 +80,7 @@ class dimm_module_decoder /// @param[out] o_output height range encoding from SPD /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode raw_card_extension(uint8_t& o_output) + virtual fapi2::ReturnCode raw_card_extension(uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -91,7 +91,7 @@ class dimm_module_decoder /// @param[out] o_output encoding from SPD /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode front_module_max_thickness(uint8_t& o_output) + virtual fapi2::ReturnCode front_module_max_thickness(uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -102,7 +102,7 @@ class dimm_module_decoder /// @param[out] o_output encoding from SPD /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode back_module_max_thickness(uint8_t& o_output) + virtual fapi2::ReturnCode back_module_max_thickness(uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -113,7 +113,7 @@ class dimm_module_decoder /// @param[out] o_output encoding from SPD /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode num_registers_used(uint8_t& o_output) + virtual fapi2::ReturnCode num_registers_used(uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -124,7 +124,7 @@ class dimm_module_decoder /// @param[out] o_output encoding from SPD /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode num_rows_of_drams(uint8_t& o_output) + virtual fapi2::ReturnCode num_rows_of_drams(uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -135,7 +135,7 @@ class dimm_module_decoder /// @param[out] o_output encoding from SPD /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode register_and_buffer_type(uint8_t& o_output) + virtual fapi2::ReturnCode register_and_buffer_type(uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -146,7 +146,7 @@ class dimm_module_decoder /// @param[out] o_output drive strength encoding from SPD /// @return FAPI2_RC_SUCCEawSS if okay /// - virtual fapi2::ReturnCode heat_spreader_thermal_char(uint8_t& o_output) + virtual fapi2::ReturnCode heat_spreader_thermal_char(uint8_t& o_output) const { // Undefined must be coded as 0x00 o_output = 0; @@ -158,7 +158,7 @@ class dimm_module_decoder /// @param[out] o_output drive strength encoding from SPD /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode heat_spreader_solution(uint8_t& o_output) + virtual fapi2::ReturnCode heat_spreader_solution(uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -169,7 +169,7 @@ class dimm_module_decoder /// @param[out] o_output drive strength encoding from SPD /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode num_continuation_codes(uint8_t& o_output) + virtual fapi2::ReturnCode num_continuation_codes(uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -180,7 +180,7 @@ class dimm_module_decoder /// @param[out] o_output drive strength encoding from SPD /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode reg_manufacturer_id_code(uint8_t& o_output) + virtual fapi2::ReturnCode reg_manufacturer_id_code(uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -191,7 +191,7 @@ class dimm_module_decoder /// @param[out] o_output drive strength encoding from SPD /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode register_rev_num(uint8_t& o_output) + virtual fapi2::ReturnCode register_rev_num(uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -202,7 +202,7 @@ class dimm_module_decoder /// @param[out] o_output drive strength encoding from SPD /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode register_to_dram_addr_mapping(uint8_t& o_output) + virtual fapi2::ReturnCode register_to_dram_addr_mapping(uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -213,7 +213,7 @@ class dimm_module_decoder /// @param[out] o_output encoding from SPD /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode cke_signal_output_driver(uint8_t& o_output) + virtual fapi2::ReturnCode cke_signal_output_driver(uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -224,7 +224,7 @@ class dimm_module_decoder /// @param[out] o_output encoding from SPD /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode odt_signal_output_driver(uint8_t& o_output) + virtual fapi2::ReturnCode odt_signal_output_driver(uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -235,7 +235,7 @@ class dimm_module_decoder /// @param[out] o_output drive strength encoding from SPD /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode ca_signal_output_driver(uint8_t& o_output) + virtual fapi2::ReturnCode ca_signal_output_driver(uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -246,7 +246,7 @@ class dimm_module_decoder /// @param[out] o_output encoding from SPD /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode cs_signal_output_driver(uint8_t& o_output) + virtual fapi2::ReturnCode cs_signal_output_driver(uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -257,7 +257,7 @@ class dimm_module_decoder /// @param[out] o_output drive strength encoding from SPD /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode b_side_clk_output_driver(uint8_t& o_output) + virtual fapi2::ReturnCode b_side_clk_output_driver(uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -268,7 +268,7 @@ class dimm_module_decoder /// @param[out] o_output drive strength encoding from SPD /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode a_side_clk_output_driver(uint8_t& o_output) + virtual fapi2::ReturnCode a_side_clk_output_driver(uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -279,7 +279,7 @@ class dimm_module_decoder /// @param[out] o_output encoded drive strength /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode bcom_bcke_bodt_drive_strength(uint8_t& o_output) + virtual fapi2::ReturnCode bcom_bcke_bodt_drive_strength(uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -291,7 +291,7 @@ class dimm_module_decoder /// @param[out] o_output encoded drive strength /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode bck_output_drive_strength(uint8_t& o_output) + virtual fapi2::ReturnCode bck_output_drive_strength(uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -302,7 +302,7 @@ class dimm_module_decoder /// @param[out] o_output encoded drive strength /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode slew_rate_control(uint8_t& o_output) + virtual fapi2::ReturnCode slew_rate_control(uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -313,7 +313,7 @@ class dimm_module_decoder /// @param[out] o_output revision number /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode data_buffer_rev(uint8_t& o_output) + virtual fapi2::ReturnCode data_buffer_rev(uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -324,7 +324,7 @@ class dimm_module_decoder /// @param[out] o_output encoding of MR6 A5:A0 in JESD790-4 spec /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode dram_vref_dq_rank0(uint8_t& o_output) + virtual fapi2::ReturnCode dram_vref_dq_rank0(uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -335,7 +335,7 @@ class dimm_module_decoder /// @param[out] o_output encoding of MR6 A5:A0 in JESD790-4 spec /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode dram_vref_dq_rank1(uint8_t& o_output) + virtual fapi2::ReturnCode dram_vref_dq_rank1(uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -346,7 +346,7 @@ class dimm_module_decoder /// @param[out] o_output encoding of MR6 A5:A0 in JESD790-4 spec /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode dram_vref_dq_rank2(uint8_t& o_output) + virtual fapi2::ReturnCode dram_vref_dq_rank2(uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -357,7 +357,7 @@ class dimm_module_decoder /// @param[out] o_output encoding of MR6 A5:A0 in JESD790-4 spec /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode dram_vref_dq_rank3(uint8_t& o_output) + virtual fapi2::ReturnCode dram_vref_dq_rank3(uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -368,7 +368,7 @@ class dimm_module_decoder /// @param[out] o_output encoding of F5BC6x in DDR4DB01 spec /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode data_buffer_vref_dq(uint8_t& o_output) + virtual fapi2::ReturnCode data_buffer_vref_dq(uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -381,7 +381,7 @@ class dimm_module_decoder /// @param[out] o_output encoding of F5BC6x in /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode data_buffer_mdq_drive_strength(const uint64_t i_dimm_speed, uint8_t& o_output) + virtual fapi2::ReturnCode data_buffer_mdq_drive_strength(const uint64_t i_dimm_speed, uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -394,7 +394,7 @@ class dimm_module_decoder /// @param[out] o_output encoding of F5BC6x in /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode data_buffer_mdq_rtt(const uint64_t i_dimm_speed, uint8_t& o_output) + virtual fapi2::ReturnCode data_buffer_mdq_rtt(const uint64_t i_dimm_speed, uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -407,7 +407,7 @@ class dimm_module_decoder /// @param[out] o_output DRAM drive strength (in ohms) /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode dram_drive_strength(const uint64_t i_dimm_speed, uint8_t& o_output) + virtual fapi2::ReturnCode dram_drive_strength(const uint64_t i_dimm_speed, uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -420,7 +420,7 @@ class dimm_module_decoder /// @param[out] o_output ODT termination strength (in ohms) /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode dram_rtt_nom(const uint64_t i_dimm_speed, uint8_t& o_output) + virtual fapi2::ReturnCode dram_rtt_nom(const uint64_t i_dimm_speed, uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -433,7 +433,7 @@ class dimm_module_decoder /// @param[out] o_output ODT termination strength (in ohms) /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode dram_rtt_wr(const uint64_t i_dimm_speed, uint8_t& o_output) + virtual fapi2::ReturnCode dram_rtt_wr(const uint64_t i_dimm_speed, uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -446,7 +446,7 @@ class dimm_module_decoder /// @param[out] o_output ODT termination strength (in ohms) /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode dram_rtt_park_ranks0_1(const uint64_t i_dimm_speed, uint8_t& o_output) + virtual fapi2::ReturnCode dram_rtt_park_ranks0_1(const uint64_t i_dimm_speed, uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -459,7 +459,7 @@ class dimm_module_decoder /// @param[out] o_output ODT termination strength (in ohms) /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode dram_rtt_park_ranks2_3(const uint64_t i_dimm_speed, uint8_t& o_output) + virtual fapi2::ReturnCode dram_rtt_park_ranks2_3(const uint64_t i_dimm_speed, uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -470,7 +470,7 @@ class dimm_module_decoder /// @param[out] o_output spd encoding /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode dram_vref_dq_range(uint8_t& o_output) + virtual fapi2::ReturnCode dram_vref_dq_range(uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -481,7 +481,7 @@ class dimm_module_decoder /// @param[out] o_output spd encoding /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode data_buffer_vref_dq_range(uint8_t& o_output) + virtual fapi2::ReturnCode data_buffer_vref_dq_range(uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -492,7 +492,7 @@ class dimm_module_decoder /// @param[out] o_output spd encoding /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode data_buffer_gain_adjustment(uint8_t& o_output) + virtual fapi2::ReturnCode data_buffer_gain_adjustment(uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -503,7 +503,7 @@ class dimm_module_decoder /// @param[out] o_output spd encoding /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode data_buffer_dfe(uint8_t& o_output) + virtual fapi2::ReturnCode data_buffer_dfe(uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; diff --git a/src/import/generic/memory/lib/spd/common/spd_decoder_base.H b/src/import/generic/memory/lib/spd/common/spd_decoder_base.H index ed67c42ac..c61983436 100644 --- a/src/import/generic/memory/lib/spd/common/spd_decoder_base.H +++ b/src/import/generic/memory/lib/spd/common/spd_decoder_base.H @@ -111,7 +111,7 @@ class decoder /// @param[out] o_logical_ranks number of logical ranks /// @return fapi2::FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode prim_sdram_logical_ranks( uint8_t& o_logical_ranks ) + virtual fapi2::ReturnCode prim_sdram_logical_ranks( uint8_t& o_logical_ranks ) const { o_logical_ranks = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -122,7 +122,7 @@ class decoder /// @param[out] o_logical_ranks number of logical ranks /// @return fapi2::FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode sec_sdram_logical_ranks( uint8_t& o_logical_ranks ) + virtual fapi2::ReturnCode sec_sdram_logical_ranks( uint8_t& o_logical_ranks ) const { o_logical_ranks = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -170,7 +170,7 @@ class decoder /// @param[out] o_value number of SPD bytes used /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode number_of_used_bytes( uint16_t& o_value ) + virtual fapi2::ReturnCode number_of_used_bytes( uint16_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -181,7 +181,7 @@ class decoder /// @param[out] o_value number of total SPD bytes /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode number_of_total_bytes( uint16_t& o_value ) + virtual fapi2::ReturnCode number_of_total_bytes( uint16_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -192,7 +192,7 @@ class decoder /// @param[out] o_value hybrid media decoding /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode hybrid_media( uint8_t& o_value ) + virtual fapi2::ReturnCode hybrid_media( uint8_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -203,7 +203,7 @@ class decoder /// @param[out] o_value hybrid decoding /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode hybrid( uint8_t& o_value ) + virtual fapi2::ReturnCode hybrid( uint8_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -214,7 +214,7 @@ class decoder /// @param[out] o_value SDRAM density in GBs /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode sdram_density( uint8_t& o_value ) + virtual fapi2::ReturnCode sdram_density( uint8_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -225,7 +225,7 @@ class decoder /// @param[out] o_value Number of SDRAM bank bits /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode bank_bits( uint8_t& o_value ) + virtual fapi2::ReturnCode bank_bits( uint8_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -236,7 +236,7 @@ class decoder /// @param[out] o_value Number of SDRAM bank groups bits /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode bank_group_bits( uint8_t& o_value ) + virtual fapi2::ReturnCode bank_group_bits( uint8_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -247,7 +247,7 @@ class decoder /// @param[out] o_value Number of SDRAM bank bits /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode column_address_bits( uint8_t& o_value ) + virtual fapi2::ReturnCode column_address_bits( uint8_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -258,7 +258,7 @@ class decoder /// @param[out] o_value Number of SDRAM bank bits /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode row_address_bits( uint8_t& o_value ) + virtual fapi2::ReturnCode row_address_bits( uint8_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -269,7 +269,7 @@ class decoder /// @param[out] o_value Number of SDRAM bank bits /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode prim_sdram_signal_loading( uint8_t& o_value ) + virtual fapi2::ReturnCode prim_sdram_signal_loading( uint8_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -280,7 +280,7 @@ class decoder /// @param[out] o_value Number of SDRAM bank bits /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode prim_sdram_die_count( uint8_t& o_value ) + virtual fapi2::ReturnCode prim_sdram_die_count( uint8_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -290,7 +290,7 @@ class decoder /// @brief Decodes Primary SDRAM package type /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode prim_sdram_package_type( uint8_t& o_value ) + virtual fapi2::ReturnCode prim_sdram_package_type( uint8_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -300,7 +300,7 @@ class decoder /// @brief Decode SDRAM Maximum activate count /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode maximum_activate_count( uint32_t& o_value ) + virtual fapi2::ReturnCode maximum_activate_count( uint32_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -310,7 +310,7 @@ class decoder /// @brief Decode SDRAM Maximum activate window (multiplier), tREFI uknown at this point /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode maximum_activate_window_multiplier( uint32_t& o_value ) + virtual fapi2::ReturnCode maximum_activate_window_multiplier( uint32_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -320,7 +320,7 @@ class decoder /// @brief Decode Post package repair (PPR) /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode post_package_repair( uint8_t& o_value ) + virtual fapi2::ReturnCode post_package_repair( uint8_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -330,7 +330,7 @@ class decoder /// @brief Decode Soft post package repair (soft PPR) /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode soft_post_package_repair( uint8_t& o_value ) + virtual fapi2::ReturnCode soft_post_package_repair( uint8_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -340,7 +340,7 @@ class decoder /// @brief Decodes Secondary SDRAM signal loading /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode sec_sdram_signal_loading( uint8_t& o_value ) + virtual fapi2::ReturnCode sec_sdram_signal_loading( uint8_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -350,7 +350,7 @@ class decoder /// @brief Decodes Secondary DRAM Density Ratio /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode sec_dram_density_ratio( uint8_t& o_value ) + virtual fapi2::ReturnCode sec_dram_density_ratio( uint8_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -360,7 +360,7 @@ class decoder /// @brief Decodes Secondary SDRAM die count /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode sec_sdram_die_count( uint8_t& o_value ) + virtual fapi2::ReturnCode sec_sdram_die_count( uint8_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -370,7 +370,7 @@ class decoder /// @brief Decodes Secondary SDRAM package type /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode sec_sdram_package_type( uint8_t& o_value ) + virtual fapi2::ReturnCode sec_sdram_package_type( uint8_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -381,7 +381,7 @@ class decoder /// @param[out] o_value enum representing if 1.2V is operable /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode operable_nominal_voltage( uint8_t& o_value ) + virtual fapi2::ReturnCode operable_nominal_voltage( uint8_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -392,7 +392,7 @@ class decoder /// @param[out] o_value enum representing if 1.2V is endurant /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode endurant_nominal_voltage( uint8_t& o_value ) + virtual fapi2::ReturnCode endurant_nominal_voltage( uint8_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -402,7 +402,7 @@ class decoder /// @param[out] o_value device width in bits /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode device_width( uint8_t& o_value ) + virtual fapi2::ReturnCode device_width( uint8_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -413,7 +413,7 @@ class decoder /// @param[out] o_value number of package ranks per DIMM /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode num_package_ranks_per_dimm( uint8_t& o_value ) + virtual fapi2::ReturnCode num_package_ranks_per_dimm( uint8_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -424,7 +424,7 @@ class decoder /// @param[out] o_value rank mix value from SPD /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode rank_mix( uint8_t& o_value ) + virtual fapi2::ReturnCode rank_mix( uint8_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -435,7 +435,7 @@ class decoder /// @param[out] o_value primary bus width in bits /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode prim_bus_width( uint8_t& o_value ) + virtual fapi2::ReturnCode prim_bus_width( uint8_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -446,7 +446,7 @@ class decoder /// @param[out] o_value bus width extension in bits /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode bus_width_extension( uint8_t& o_value ) + virtual fapi2::ReturnCode bus_width_extension( uint8_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -457,7 +457,7 @@ class decoder /// @param[out] o_value thermal sensor value from SPD /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode thermal_sensor( uint8_t& o_value ) + virtual fapi2::ReturnCode thermal_sensor( uint8_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -468,7 +468,7 @@ class decoder /// @param[out] o_value extended base module type value from SPD /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode extended_base_module_type( uint8_t& o_value ) + virtual fapi2::ReturnCode extended_base_module_type( uint8_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -479,7 +479,7 @@ class decoder /// @param[out] o_value fine_timebase from SPD in picoseconds /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode fine_timebase( int64_t& o_value ) + virtual fapi2::ReturnCode fine_timebase( int64_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -490,7 +490,7 @@ class decoder /// @param[out] o_value fine_timebase from SPD in picoseconds /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode medium_timebase( int64_t& o_value ) + virtual fapi2::ReturnCode medium_timebase( int64_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -502,7 +502,7 @@ class decoder /// @param[out] o_value tCKmin in MTB units /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode min_tck( int64_t& o_value ) + virtual fapi2::ReturnCode min_tck( int64_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -513,7 +513,7 @@ class decoder /// @param[out] o_value tCKmax in MTB units /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode max_tck( int64_t& o_value ) + virtual fapi2::ReturnCode max_tck( int64_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -524,7 +524,7 @@ class decoder /// @param[out] o_value bitmap of supported CAS latencies /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode supported_cas_latencies( uint64_t& o_value ) + virtual fapi2::ReturnCode supported_cas_latencies( uint64_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -535,7 +535,7 @@ class decoder /// @param[out] o_value tAAmin in MTB units /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode min_taa( int64_t& o_value ) + virtual fapi2::ReturnCode min_taa( int64_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -546,7 +546,7 @@ class decoder /// @param[out] o_value tRCDmin in MTB units /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode min_trcd( int64_t& o_value ) + virtual fapi2::ReturnCode min_trcd( int64_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -557,7 +557,7 @@ class decoder /// @param[out] o_value tRPmin in MTB units /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode min_trp( int64_t& o_value ) + virtual fapi2::ReturnCode min_trp( int64_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -568,7 +568,7 @@ class decoder /// @param[out] o_value tRASmin in MTB units /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode min_tras( int64_t& o_value ) + virtual fapi2::ReturnCode min_tras( int64_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -579,7 +579,7 @@ class decoder /// @param[out] o_value tRCmin in MTB units /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode min_trc( int64_t& o_value ) + virtual fapi2::ReturnCode min_trc( int64_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -590,7 +590,7 @@ class decoder /// @param[out] o_value tRFC1min in MTB units /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode min_trfc1( int64_t& o_value ) + virtual fapi2::ReturnCode min_trfc1( int64_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -601,7 +601,7 @@ class decoder /// @param[out] o_value tRFC2min in MTB units /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode min_trfc2( int64_t& o_value ) + virtual fapi2::ReturnCode min_trfc2( int64_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -612,7 +612,7 @@ class decoder /// @param[out] o_value tRFC4min in MTB units /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode min_trfc4( int64_t& o_value ) + virtual fapi2::ReturnCode min_trfc4( int64_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -623,7 +623,7 @@ class decoder /// @param[out] o_value tFAWmin in MTB units /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode min_tfaw( int64_t& o_value ) + virtual fapi2::ReturnCode min_tfaw( int64_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -634,7 +634,7 @@ class decoder /// @param[out] o_value tRRD_Smin MTB units /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode min_trrd_s( int64_t& o_value ) + virtual fapi2::ReturnCode min_trrd_s( int64_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -645,7 +645,7 @@ class decoder /// @param[out] o_value tRRD_Lmin MTB units /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode min_trrd_l( int64_t& o_value ) + virtual fapi2::ReturnCode min_trrd_l( int64_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -656,7 +656,7 @@ class decoder /// @param[out] o_value tCCD_Lmin MTB units /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode min_tccd_l( int64_t& o_value ) + virtual fapi2::ReturnCode min_tccd_l( int64_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -667,7 +667,7 @@ class decoder /// @param[out] o_value tWRmin in MTB units /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode min_twr( int64_t& o_value ) + virtual fapi2::ReturnCode min_twr( int64_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -678,7 +678,7 @@ class decoder /// @param[out] o_value tWRT_Smin in MTB units /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode min_twtr_s( int64_t& o_value ) + virtual fapi2::ReturnCode min_twtr_s( int64_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -689,7 +689,7 @@ class decoder /// @param[out] o_value tWRT_Lmin in MTB units /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode min_twtr_l( int64_t& o_value ) + virtual fapi2::ReturnCode min_twtr_l( int64_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -700,7 +700,7 @@ class decoder /// @param[out] o_value tCCD_Lmin offset in FTB units /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode fine_offset_min_tccd_l( int64_t& o_value ) + virtual fapi2::ReturnCode fine_offset_min_tccd_l( int64_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -711,7 +711,7 @@ class decoder /// @param[out] o_value tRRD_Lmin offset in FTB units /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode fine_offset_min_trrd_l( int64_t& o_value ) + virtual fapi2::ReturnCode fine_offset_min_trrd_l( int64_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -722,7 +722,7 @@ class decoder /// @param[out] o_value tRRD_Smin offset in FTB units /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode fine_offset_min_trrd_s( int64_t& o_value ) + virtual fapi2::ReturnCode fine_offset_min_trrd_s( int64_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -733,7 +733,7 @@ class decoder /// @param[out] o_value tRCmin offset in FTB units /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode fine_offset_min_trc( int64_t& o_value ) + virtual fapi2::ReturnCode fine_offset_min_trc( int64_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -744,7 +744,7 @@ class decoder /// @param[out] o_value tRPmin offset in FTB units /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode fine_offset_min_trp( int64_t& o_value ) + virtual fapi2::ReturnCode fine_offset_min_trp( int64_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -755,7 +755,7 @@ class decoder /// @param[out] o_value tRCDmin offset in FTB units /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode fine_offset_min_trcd( int64_t& o_value ) + virtual fapi2::ReturnCode fine_offset_min_trcd( int64_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -766,7 +766,7 @@ class decoder /// @param[out] o_value tAAmin offset in FTB units /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode fine_offset_min_taa( int64_t& o_value ) + virtual fapi2::ReturnCode fine_offset_min_taa( int64_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -777,7 +777,7 @@ class decoder /// @param[out] o_value tCKmax offset in FTB units /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode fine_offset_max_tck( int64_t& o_value ) + virtual fapi2::ReturnCode fine_offset_max_tck( int64_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -788,7 +788,7 @@ class decoder /// @param[out] o_value tCKmin offset in FTB units /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode fine_offset_min_tck( int64_t& o_value ) + virtual fapi2::ReturnCode fine_offset_min_tck( int64_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -799,7 +799,7 @@ class decoder /// @param[out] o_value crc value from SPD /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode cyclical_redundancy_code( uint16_t& o_value ) + virtual fapi2::ReturnCode cyclical_redundancy_code( uint16_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -810,7 +810,7 @@ class decoder /// @param[out] o_output module manufacturing id code /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode module_manufacturer_id_code( uint16_t& o_value ) + virtual fapi2::ReturnCode module_manufacturer_id_code( uint16_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -821,7 +821,7 @@ class decoder /// @param[out] o_value uint8_t identifier for manufacturing location of memory module /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode module_manufacturing_location( uint8_t& o_value ) + virtual fapi2::ReturnCode module_manufacturing_location( uint8_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -831,7 +831,7 @@ class decoder /// @brief Decodesmodule manufacturing date /// @param[out] o_value the 2 byte date of manufacturing in BCD format /// @return FAPI2_RC_SUCCESS if okay - virtual fapi2::ReturnCode module_manufacturing_date( uint16_t& o_value ) + virtual fapi2::ReturnCode module_manufacturing_date( uint16_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -842,7 +842,7 @@ class decoder /// @param[out] o_value module's serial number /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode module_serial_number( uint32_t& o_value ) + virtual fapi2::ReturnCode module_serial_number( uint32_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -853,7 +853,7 @@ class decoder /// @param[out] o_value uint8_t identifier for revision code /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode module_revision_code( uint8_t& o_value ) + virtual fapi2::ReturnCode module_revision_code( uint8_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -864,7 +864,7 @@ class decoder /// @param[out] o_value dram manufacturing id code /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode dram_manufacturer_id_code( uint16_t& o_value ) + virtual fapi2::ReturnCode dram_manufacturer_id_code( uint16_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -875,7 +875,7 @@ class decoder /// @param[out] o_value uint8_t DRAM Stepping val /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode dram_stepping( uint8_t& o_value ) + virtual fapi2::ReturnCode dram_stepping( uint8_t& o_value ) const { o_value = 0; return fapi2::FAPI2_RC_SUCCESS; @@ -886,7 +886,7 @@ class decoder /// @param[out] o_logical_ranks number of logical ranks /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode logical_ranks_per_dimm( uint8_t& o_logical_rank_per_dimm ) + virtual fapi2::ReturnCode logical_ranks_per_dimm( uint8_t& o_logical_rank_per_dimm ) const { o_logical_rank_per_dimm = 0; return fapi2::FAPI2_RC_SUCCESS; |
