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| author | Tsung Yeung <tyeung@us.ibm.com> | 2019-05-08 17:33:03 -0400 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2019-05-17 09:41:17 -0500 |
| commit | 2c39e6a8184b1c7d5cfab80d3d6576d86767b79a (patch) | |
| tree | 59a8b138058f13e76038579afebe5c14c5b86307 /src/import/generic/memory/lib/ccs | |
| parent | 574186ea098a9e9dbb6de4ffa44e9489f3125e01 (diff) | |
| download | talos-hostboot-2c39e6a8184b1c7d5cfab80d3d6576d86767b79a.tar.gz talos-hostboot-2c39e6a8184b1c7d5cfab80d3d6576d86767b79a.zip | |
NVDIMM wr_vref workaround fix and add refreshes to ccs program (nvdimm only)
Change-Id: I0331284a284ac54ebd365abd96c67d4094b124b8
CQ:SW463048
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77157
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77198
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/generic/memory/lib/ccs')
| -rw-r--r-- | src/import/generic/memory/lib/ccs/ccs.H | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/src/import/generic/memory/lib/ccs/ccs.H b/src/import/generic/memory/lib/ccs/ccs.H index b72ec64ae..aafb0826e 100644 --- a/src/import/generic/memory/lib/ccs/ccs.H +++ b/src/import/generic/memory/lib/ccs/ccs.H @@ -883,6 +883,29 @@ inline instruction_t self_refresh_exit_command( const uint64_t i_rank, const uin return instruction_t(i_rank, l_boilerplate_arr0, l_boilerplate_arr1); } +/// +/// @brief Setup refresh command instruction +/// @tparam T the target type of the chiplet which executes the CCS instruction +/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction +/// @param[in] i_target the DIMM this instruction is headed for +/// @param[in] i_rank the rank on this dimm +/// @param[in] i_idle the idle time to the next command (default to 0) +/// @return the self-refresh entry command CCS instruction +/// @note THIS IS FOR DDR4 NON-LRDIMM ONLY RIGHT NOW +/// +inline instruction_t refresh_command( const uint64_t i_rank, const uint16_t i_idle = 0 ) +{ + using TT = ccsTraits<DEFAULT_MC_TYPE>; + + // Refresh is self-refresh entry with CKE high + auto l_refresh_template = self_refresh_entry_command(i_rank, i_idle); + + // CKE is high + l_refresh_template.arr0.template insertFromRight<TT::ARR0_DDR_CKE, TT::ARR0_DDR_CKE_LEN>(CKE_HIGH); + + return l_refresh_template; +} + // // These functions are a little sugar to keep callers from doing the traits-dance to get the // appropriate bit field |
