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author | Stephen Glancy <sglancy@us.ibm.com> | 2018-10-08 11:00:53 -0500 |
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committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2018-10-15 16:57:33 -0500 |
commit | f3a2693e80a042b77888555106aae320cc400aca (patch) | |
tree | f9dc0567b81e95f37d3e8817bbaf944ab7d16bce /src/import/chips | |
parent | 55ff29accb8313232e5a1a6cf5d7a54681579073 (diff) | |
download | talos-hostboot-f3a2693e80a042b77888555106aae320cc400aca.tar.gz talos-hostboot-f3a2693e80a042b77888555106aae320cc400aca.zip |
Updates training steps factory to be LRDIMM capable
Change-Id: I4f8e5a071074d462817c4ba7203462443164b5a8
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67156
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67160
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips')
5 files changed, 131 insertions, 16 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.C index fb0213987..e5a3e8d66 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.C @@ -198,7 +198,36 @@ uint64_t mwd::calculate_cycles( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_t return 0; } -// TK:LRDIMM update all of this file to have the actual LRDIMM training steps +/// +/// @brief Deconfigures calibration steps depending upon LRDIMM type +/// @param[in] i_dimm_type - DIMM type +/// @param[in] i_sim - simulation mode or not +/// @param[in,out] io_cal_steps - the bit mask of calibration steps +/// @return a vector of the calibration steps to run +/// +void deconfigure_steps(const uint8_t i_dimm_type, const bool i_sim, fapi2::buffer<uint32_t>& io_cal_steps) +{ + // If the DIMM type is an LRDIMM, configure for LRDIMM + if(i_dimm_type == fapi2::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) + { + FAPI_INF("LRDIMM: deconfigure WR VREF 2D"); + // We clear WRITE_CTR_2D_VREF as the HW calibration algorithm will not work with LRDIMM + io_cal_steps.clearBit<WRITE_CTR_2D_VREF>(); + return; + } + + FAPI_INF("Not LRDIMM: deconfigure all LRDIMM specific steps"); + // Otherwise, clear all LRDIMM calibration steps + io_cal_steps.clearBit<DB_ZQCAL>() + .clearBit<MREP>() + .clearBit<MRD_COARSE>() + .clearBit<MRD_FINE>() + .clearBit<DWL>() + .clearBit<MWD_COARSE>() + .clearBit<MWD_FINE>() + .clearBit<HWL>(); +} + } // ns lrdimm diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.H index a1c9377b3..e798839f8 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.H @@ -233,6 +233,15 @@ class mwd : public step // TK:LRDIMM Identify if Host Interface Read Training is any different // TK:LRDIMM Identify if Host Interface Write training Training is any different +/// +/// @brief Deconfigures calibration steps depending upon LRDIMM type +/// @param[in] i_dimm_type - DIMM type +/// @param[in] i_sim - simulation mode or not +/// @param[in,out] io_cal_steps - the bit mask of calibration steps +/// @return a vector of the calibration steps to run +/// +void deconfigure_steps(const uint8_t i_dimm_type, const bool i_sim, fapi2::buffer<uint32_t>& io_cal_steps); + } // ns training } // ns lrdimm diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C index da4f2a359..d6e9d06ec 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C @@ -1211,9 +1211,16 @@ fapi_try_exit: /// std::vector<std::shared_ptr<step>> steps_factory(const fapi2::buffer<uint32_t>& i_cal_steps, const bool i_sim) { - // TK:LRDIMM Update the factory to add in LRDIMM training steps + FAPI_INF("Running factory for cal_steps:0x%08x %s mode", i_cal_steps, i_sim ? "simulation" : "hardware"); std::vector<std::shared_ptr<step>> l_steps; + // MREP + if(i_cal_steps.getBit<mss::cal_steps::MREP>()) + { + FAPI_INF("LRDIMM: MREP is enabled"); + l_steps.push_back(std::make_shared<mss::training::lrdimm::mrep>()); + } + // WR LVL if(i_cal_steps.getBit<mss::cal_steps::WR_LEVEL>()) { @@ -1222,17 +1229,11 @@ std::vector<std::shared_ptr<step>> steps_factory(const fapi2::buffer<uint32_t>& } // INITIAL_PAT_WR - // Note: simulation contains a bug where the DDR4 model does not match the DDR4 hardware - // As such, if the simulation IPW bug is set, do not create a step for initial pattern write - if(!i_sim && i_cal_steps.getBit<mss::cal_steps::INITIAL_PAT_WR>()) + if(i_cal_steps.getBit<mss::cal_steps::INITIAL_PAT_WR>()) { FAPI_INF("Initial pattern write is enabled"); l_steps.push_back(std::make_shared<initial_pattern_write>()); } - else if(i_sim) - { - FAPI_INF("Initial pattern write was requested, but the simulation for it is bugged! Skipping IPW"); - } // DQS_ALIGN if(i_cal_steps.getBit<mss::cal_steps::DQS_ALIGN>()) @@ -1273,7 +1274,6 @@ std::vector<std::shared_ptr<step>> steps_factory(const fapi2::buffer<uint32_t>& l_steps.push_back(std::make_shared<wr_vref_latch>( WR_VREF )); } - // WRITE_CTR_2D_VREF or WRITE_CTR if(WR_VREF || WRITE_CTR) { @@ -1290,17 +1290,14 @@ std::vector<std::shared_ptr<step>> steps_factory(const fapi2::buffer<uint32_t>& l_steps.push_back(std::make_shared<coarse_wr_rd>()); } - // We can't run custom pattern RD as it requires initial pattern write, so skipping it in SIM mode - const bool CUSTOM_RD = (!i_sim) && i_cal_steps.getBit<mss::cal_steps::TRAINING_ADV_RD>(); - // Run custom WR CTR and custom RD CTR together - if(CUSTOM_RD && i_cal_steps.getBit<mss::cal_steps::TRAINING_ADV_WR>()) + if(i_cal_steps.getBit<mss::cal_steps::TRAINING_ADV_RD>() && i_cal_steps.getBit<mss::cal_steps::TRAINING_ADV_WR>()) { FAPI_INF("Custom RD_CTR and Custom WR_CTR are enabled"); l_steps.push_back(std::make_shared<custom_training_facade>()); } // Training Advanced Read - aka custom pattern RD CTR - else if(CUSTOM_RD) + else if(i_cal_steps.getBit<mss::cal_steps::TRAINING_ADV_RD>()) { FAPI_INF("Custom RD_CTR is enabled"); l_steps.push_back(std::make_shared<custom_read_ctr>()); @@ -1316,6 +1313,62 @@ std::vector<std::shared_ptr<step>> steps_factory(const fapi2::buffer<uint32_t>& return l_steps; } +/// +/// @brief Creates the vector of training steps to loop over with an LRDIMM switch included +/// @param[in] i_dimm_type - the DIMM type - used to select LRDIMM vs not +/// @param[in] i_cal_steps - the bit mask of calibration steps +/// @param[in] i_sim - simulation mode or not +/// @return a vector of the calibration steps to run +/// +std::vector<std::shared_ptr<step>> steps_factory(const uint8_t i_dimm_type, const fapi2::buffer<uint32_t>& i_cal_steps, + const bool i_sim) +{ + // We need to modify the calibration steps, so create a copy + auto l_cal_steps = i_cal_steps; + + // Deconfigure based upon DIMM type (don't run LR if we're not LR) + mss::training::lrdimm::deconfigure_steps(i_dimm_type, i_sim, l_cal_steps); + + // Deconfigure based upon simulation mode + sim::deconfigure_steps(i_sim, l_cal_steps); + + // Print the configured calibration steps + FAPI_INF("Configured calibration steps are 0x%08x for DIMM type: %u %s mode", + l_cal_steps, i_dimm_type, i_sim ? "simulation" : "hardware"); + + // Run the standard factory + return steps_factory(l_cal_steps, i_sim); +} + +namespace sim +{ + +/// +/// @brief Deconfigures steps based upon simulation mode +/// @param[in] i_sim - simulation mode or not +/// @param[in,out] io_cal_steps calibration steps to deconfigure +/// +void deconfigure_steps(const bool i_sim, fapi2::buffer<uint32_t>& io_cal_steps) +{ + // If we're not in sim mode, everything can run a-ok + if(!i_sim) + { + FAPI_INF("We're not in simulation mode, we can run with all configured steps"); + return; + } + + FAPI_INF("In simulation mode. Deconfiguring initial pattern write and training advanced read"); + // Otherwise, deconfigure those steps + // Note: simulation contains a bug where the DDR4 model does not match the DDR4 hardware + // As such, if the simulation IPW bug is set, do not create a step for initial pattern write + io_cal_steps.clearBit<mss::cal_steps::INITIAL_PAT_WR>(); + + // We can't run custom pattern RD as it requires initial pattern write, so skipping it in SIM mode + io_cal_steps.clearBit<mss::cal_steps::TRAINING_ADV_RD>(); +} + +} // ns sim + } // ns training } // ns mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.H index c8b9fdeef..714dfae3a 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.H @@ -903,6 +903,25 @@ class custom_training_facade : public step /// std::vector<std::shared_ptr<step>> steps_factory(const fapi2::buffer<uint32_t>& i_cal_steps, const bool i_sim); +/// +/// @brief Creates the vector of training steps to loop over with an LRDIMM switch included +/// @param[in] i_dimm_type - the DIMM type - used to select LRDIMM vs not +/// @param[in] i_cal_steps - the bit mask of calibration steps +/// @param[in] i_sim - simulation mode or not +/// @return a vector of the calibration steps to run +/// +std::vector<std::shared_ptr<step>> steps_factory(const uint8_t i_dimm_type, const fapi2::buffer<uint32_t>& i_cal_steps, + const bool i_sim); +namespace sim +{ +/// +/// @brief Deconfigures steps based upon simulation mode +/// @param[in] i_sim - simulation mode or not +/// @param[in,out] io_cal_steps calibration steps to deconfigure +/// +void deconfigure_steps(const bool i_sim, fapi2::buffer<uint32_t>& io_cal_steps); +} // ns sim + } // ns training } // ns mss diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C index a3682dff6..45d8cbcd5 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C @@ -120,6 +120,10 @@ extern "C" // we configured on this port. std::vector<uint64_t> l_pairs; + // DIMM type + uint8_t l_dimm_type[mss::MAX_DIMM_PER_PORT] = {}; + FAPI_TRY(mss::eff_dimm_type(p, &l_dimm_type[0]), "%s failed to access DIMM type", mss::c_str(p)); + // Grab the attribute which contains the information on what cal steps we should run // if the i_specal_training bits have not been specified. if (i_special_training == 0) @@ -181,7 +185,8 @@ extern "C" bool l_cal_fail = false; FAPI_INF("Execute cal on rp %d %s", rp, mss::c_str(p)); - for(const auto& l_step : mss::training::steps_factory(l_cal_steps_enabled, l_sim)) + // Per plug rules, mixing LRDIMM and RDIMM shouldn't be allowed, so we're ok grabbing the value from DIMM0 + for(const auto& l_step : mss::training::steps_factory(l_dimm_type[0], l_cal_steps_enabled, l_sim)) { FAPI_TRY( l_step->execute( p, rp, l_cal_abort_on_error) ); } |