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authorJacob Harvey <jlharvey@us.ibm.com>2017-03-07 11:43:00 -0600
committerDaniel M. Crowell <dcrowell@us.ibm.com>2017-04-07 14:28:52 -0400
commitecc3ff1845dfebcc43aca14b76011e4e0563cc94 (patch)
tree3564e99df3e808db4b0576f6f3396e923763b98f /src/import/chips
parentb96a2fb8b1ba8217224c2d3f6c19fdd06a973481 (diff)
downloadtalos-hostboot-ecc3ff1845dfebcc43aca14b76011e4e0563cc94.tar.gz
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Change accesses to IS_SIM to use mss accessor
Change-Id: Ice151f9f732c04160247ac153b656cdf8629f5d7 Original-Change-Id: Iafcaddbca510c29fb4a0289490b90b539dde2b13 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37610 Reviewed-by: Brian R. Silver <bsilver@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38762 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips')
-rw-r--r--src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H
index 8ea892a33..1b70a1b0e 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H
@@ -364,7 +364,7 @@ inline fapi2::ReturnCode reset_config2( const fapi2::Target<T>& i_target )
fapi2::buffer<uint64_t> l_data;
// Bogus Centaur SIM number from init file - use 8 per Bialas 2/16
- // ---48:52, 0b00000, (def_is_sim); # CONSEQ_PASS sim value---
+ // ---48:52, 0b00000, (def_l_sim); # CONSEQ_PASS sim value---
// 48:52, 0b01000, (def_is_bl8); # CONSEQ_PASS 8 from SWyatt
// 48:52, 0b01111, any; # CONSEQ_PASS 16 min for BL4, or OTF
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