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author | Louis Stermole <stermole@us.ibm.com> | 2016-08-10 15:04:32 -0500 |
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committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-08-25 16:38:42 -0400 |
commit | e73c4129fc3da8761d75d10cb9a69a8d85f74002 (patch) | |
tree | 86a70383e0dad405e2d236ae538f31365cd2ad87 /src/import/chips | |
parent | 80eff827ef7c9d4f56cf56e0a143490963973cf5 (diff) | |
download | talos-hostboot-e73c4129fc3da8761d75d10cb9a69a8d85f74002.tar.gz talos-hostboot-e73c4129fc3da8761d75d10cb9a69a8d85f74002.zip |
Change DRAM output impedance value to be from MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS
Change-Id: I146ff2adbaa96d7b0ae34c4fdde6b6fde3c34f5e
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28147
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28148
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips')
5 files changed, 12 insertions, 47 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C index 71f1fa0d5..f4a25496a 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C @@ -56,14 +56,13 @@ namespace ddr4 /// mrs01_data::mrs01_data( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, fapi2::ReturnCode& o_rc ): iv_dll_enable(fapi2::ENUM_ATTR_EFF_DRAM_DLL_ENABLE_YES), - iv_odic(0), iv_additive_latency(0), iv_wl_enable(0), iv_tdqs(0), iv_qoff(0) { FAPI_TRY( mss::eff_dram_dll_enable(i_target, iv_dll_enable) ); - FAPI_TRY( mss::eff_dram_ron(i_target, iv_odic) ); + FAPI_TRY( mss::vpd_mt_dram_drv_imp_dq_dqs(i_target, &(iv_odic[0])) ); FAPI_TRY( mss::eff_dram_al(i_target, iv_additive_latency) ); FAPI_TRY( mss::eff_dram_wr_lvl_enable(i_target, iv_wl_enable) ); FAPI_TRY( mss::vpd_mt_dram_rtt_nom(i_target, &(iv_rtt_nom[0])) ); @@ -129,17 +128,18 @@ fapi2::ReturnCode mrs01(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, fapi2::buffer<uint8_t> l_odic_buffer; fapi2::buffer<uint8_t> l_rtt_nom_buffer; - FAPI_ASSERT( ((i_data.iv_odic == fapi2::ENUM_ATTR_EFF_DRAM_RON_OHM34) || - (i_data.iv_odic == fapi2::ENUM_ATTR_EFF_DRAM_RON_OHM48)), + FAPI_ASSERT( ((i_data.iv_odic[mss::index(i_rank)] == fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS_OHM34) || + (i_data.iv_odic[mss::index(i_rank)] == fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS_OHM48)), fapi2::MSS_BAD_MR_PARAMETER() .set_MR_NUMBER(1) .set_PARAMETER(OUTPUT_IMPEDANCE) - .set_PARAMETER_VALUE(i_data.iv_odic) + .set_PARAMETER_VALUE(i_data.iv_odic[mss::index(i_rank)]) .set_DIMM_IN_ERROR(i_target), - "Bad value for output driver impedance: %d (%s)", i_data.iv_odic, mss::c_str(i_target)); + "Bad value for output driver impedance: %d (%s)", i_data.iv_odic[mss::index(i_rank)], mss::c_str(i_target)); // Map from impedance to bits in MRS1 - l_odic_buffer = (i_data.iv_odic == fapi2::ENUM_ATTR_EFF_DRAM_RON_OHM34) ? odic_map[0] : odic_map[1]; + l_odic_buffer = (i_data.iv_odic[mss::index(i_rank)] == fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS_OHM34) ? + odic_map[0] : odic_map[1]; // We have to be careful about 0 l_rtt_nom_index = (i_data.iv_rtt_nom[mss::index(i_rank)] == 0) ? @@ -151,7 +151,8 @@ fapi2::ReturnCode mrs01(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, // Print this here as opposed to the MRS01 ctor as we want to see the specific rtt now information FAPI_INF("MR1 rank %d attributes: DLL_ENABLE: 0x%x, ODIC: 0x%x(0x%x), AL: 0x%x, WLE: 0x%x, " "RTT_NOM: 0x%x(0x%x), TDQS: 0x%x, QOFF: 0x%x", i_rank, - i_data.iv_dll_enable, i_data.iv_odic, uint8_t(l_odic_buffer), uint8_t(l_additive_latency), i_data.iv_wl_enable, + i_data.iv_dll_enable, i_data.iv_odic[mss::index(i_rank)], uint8_t(l_odic_buffer), uint8_t(l_additive_latency), + i_data.iv_wl_enable, i_data.iv_rtt_nom[mss::index(i_rank)], uint8_t(l_rtt_nom_buffer), i_data.iv_tdqs, i_data.iv_qoff); io_inst.arr0.writeBit<A0>(i_data.iv_dll_enable); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H index dbb613186..c06ad6c3c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H @@ -378,7 +378,7 @@ struct mrs01_data mrs01_data( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, fapi2::ReturnCode& o_rc ); uint8_t iv_dll_enable; - uint8_t iv_odic; + uint8_t iv_odic[MAX_RANK_PER_DIMM]; uint8_t iv_additive_latency; uint8_t iv_wl_enable; uint8_t iv_tdqs; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C index d8eca636d..f98503010 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C @@ -1726,35 +1726,6 @@ fapi_try_exit: } /// -/// @brief Determines & sets effective config for RON -/// @param[in] i_target FAPI2 target -/// @return fapi2::FAPI2_RC_SUCCESS if okay -/// -fapi2::ReturnCode eff_config::dram_ron(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) -{ - // TK - RIT skeleton. Need to finish - AAM - uint8_t l_attrs_dram_ron[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {}; - - // Targets - const auto l_mcs = find_target<TARGET_TYPE_MCS>(i_target); - const auto l_mca = find_target<TARGET_TYPE_MCA>(i_target); - - // Current index - const auto l_port_num = index(l_mca); - const auto l_dimm_num = index(i_target); - - FAPI_TRY( eff_dram_ron(l_mcs, &l_attrs_dram_ron[0][0]) ); - - l_attrs_dram_ron[l_port_num][l_dimm_num] = 0x22; - - FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_RON, l_mcs, l_attrs_dram_ron), - "Failed setting attribute for BL"); - -fapi_try_exit: - return fapi2::current_err; -} - -/// /// @brief Determines & sets effective config for Write Level Enable /// @param[in] i_target FAPI2 target /// @return fapi2::FAPI2_RC_SUCCESS if okay @@ -2467,7 +2438,8 @@ fapi2::ReturnCode eff_config::crc_wr_latency(const fapi2::Target<TARGET_TYPE_DIM //5 - 1866, 2133, 2400 //6 - TBD //Nimbus only supports 1866->2400 on the current list - //2667 is not noted. as such, alway setting crc_wr_latency to 0x05 until JEDEC value is updated + //2667 is not noted. We will set crc_wr_latency to 0x05 until JEDEC value is updated + //When JEDEC defines the 2667 value we can change this, but leave the sim value as 0x05 l_attrs_crc_wr_latency[l_port_num] = 0x05; } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.H b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.H index a2b1c79d7..ec4e34753 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.H @@ -461,13 +461,6 @@ class eff_config fapi2::ReturnCode dll_enable(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target); /// - /// @brief Determines & sets effective config for RON - /// @param[in] i_target FAPI2 target - /// @return fapi2::FAPI2_RC_SUCCESS if okay - /// - fapi2::ReturnCode dram_ron(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target); - - /// /// @brief Determines & sets effective config for Write Level Enable /// @param[in] i_target FAPI2 target /// @return fapi2::FAPI2_RC_SUCCESS if okay diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C index 729f3b438..fd1c98256 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C @@ -161,7 +161,6 @@ fapi2::ReturnCode p9_mss_eff_config( const fapi2::Target<fapi2::TARGET_TYPE_MCS> FAPI_TRY( l_eff_config.additive_latency(l_dimm) ); FAPI_TRY( l_eff_config.dll_enable(l_dimm) ); FAPI_TRY( l_eff_config.dll_reset(l_dimm) ); - FAPI_TRY( l_eff_config.dram_ron(l_dimm) ); FAPI_TRY( l_eff_config.write_level_enable(l_dimm) ); FAPI_TRY( l_eff_config.output_buffer(l_dimm) ); FAPI_TRY( l_eff_config.vref_dq_train_value(l_dimm) ); |