Adding SCOM addr translation for PPE chip units

Change-Id: I708ba2769358c606e1ea7aa36436c7ee7d2c945b
RTC: 137093
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27147
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Dev-Ready: Brent Wieman <bwieman@us.ibm.com>
Reviewed-by: Brent Wieman <bwieman@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27151
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

3 files changed, 282 insertions, 44 deletions

diff --git a/src/import/chips/p9/common/scominfo/p9_cu.H b/src/import/chips/p9/common/scominfo/p9_cu.H
index c785c5b6c..6ae5017f5 100644
--- a/src/import/chips/p9/common/scominfo/p9_cu.H
+++ b/src/import/chips/p9/common/scominfo/p9_cu.H
@@ -23,7 +23,7 @@
 /// HWP HWP Owner: jmcgill@us.ibm.com
 /// HWP FW Owner: dcrowell@us.ibm.com
 /// HWP Team: Infrastructure
-/// HWP Level: 1
+/// HWP Level: 2
 /// HWP Consumed by: FSP/HB
 ///
 
@@ -53,13 +53,11 @@ extern "C"
         PU_MCS_CHIPUNIT,     ///< MCS (Nimbus only)
         PU_MCA_CHIPUNIT,     ///< MCA (Nimbus only)
         PU_MCBIST_CHIPUNIT,  ///< MCBIST (Nimbus only)
-        PU_OCC_CHIPUNIT,     ///< OCC
         PU_PERV_CHIPUNIT,    ///< Pervasive
         PU_PPE_CHIPUNIT,     ///< PPE
         PU_SBE_CHIPUNIT,     ///< SBE
         PU_CAPP_CHIPUNIT,    ///< CAPP
-        NONE,                 ///< None/Invalid
-        PU_NVBUS_CHIPUNIT =  PU_NV_CHIPUNIT  ///< DO NOT USE!  TEMPORARY FOR CI ONLY
+        NONE,                ///< None/Invalid
     } p9ChipUnits_t;
 
     /// P9 chip unit pairing struct
@@ -76,6 +74,34 @@ extern "C"
         uint32_t chipUnitNum;        ///< chip unit instance number
     };
 
+    /// P9 PPE Chip Unit Instance Number enumeration
+    /// PPE name        Nimbus    Cumulus
+    /// SBE             0         0
+    /// GPE0..3         10..13    10..13
+    /// CME0            20..25    20..25
+    /// CME1            30..35    30..35
+    /// IO PPE (xbus)   40        40
+    /// IO PPE (obus)   41,42     41,42
+    /// IO PPE (dmi)    NA        43,44
+    /// Powerbus PPEs   50        50..52
+    typedef enum
+    {
+        PPE_SBE_CHIPUNIT_NUM         =  0,
+        PPE_GPE0_CHIPUNIT_NUM        = 10,
+        PPE_GPE3_CHIPUNIT_NUM        = 13,
+        PPE_EQ0_CME0_CHIPUNIT_NUM    = 20,   // Quad0-CME0
+        PPE_EQ5_CME0_CHIPUNIT_NUM    = 25,   // Quad5-CME0
+        PPE_EQ0_CME1_CHIPUNIT_NUM    = 30,   // Quad0-CME1
+        PPE_EQ5_CME1_CHIPUNIT_NUM    = 35,   // Quad5-CME1
+        PPE_IO_XBUS_CHIPUNIT_NUM     = 40,
+        PPE_IO_OB0_CHIPUNIT_NUM      = 41,
+        PPE_IO_OB1_CHIPUNIT_NUM      = 42,
+        PPE_IO1_DMI_CHIPUNIT_NUM     = 44,
+        PPE_PB0_CHIPUNIT_NUM         = 50,
+        PPE_PB2_CHIPUNIT_NUM         = 52,
+        PPE_LAST_CHIPUNIT_NUM        = PPE_PB2_CHIPUNIT_NUM,
+    } p9_ppe_chip_unit_instance_num_t;
+
 } // extern "C"
 
 #endif /* P9_CU_H */
diff --git a/src/import/chips/p9/common/scominfo/p9_scom_addr.H b/src/import/chips/p9/common/scominfo/p9_scom_addr.H
index 392631f8d..bdd1000dc 100644
--- a/src/import/chips/p9/common/scominfo/p9_scom_addr.H
+++ b/src/import/chips/p9/common/scominfo/p9_scom_addr.H
@@ -17,13 +17,13 @@
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
 ///
-/// @file p9_cu.H
-/// @brief P9 chip unit definitions
+/// @file p9_scom_addr.H
+/// @brief P9 SCOM address class
 ///
 /// HWP HWP Owner: jmcgill@us.ibm.com
 /// HWP FW Owner: dcrowell@us.ibm.com
 /// HWP Team: Infrastructure
-/// HWP Level: 1
+/// HWP Level: 2
 /// HWP Consumed by: FSP/HB
 ///
 
@@ -106,6 +106,8 @@ extern "C"
         CC_PORT_ID = 0x3,           ///< Clock control registers
         FIR_PORT_ID = 0x4,          ///< Common FIR registers
         CPM_PORT_ID = 0x5,          ///< CPM registers
+        GPE_PORT_ID = 0x6,          ///< PPE GPE registers (For TP only)
+        SBE_PORT_ID = 0xE,          ///< SBE PM registers (For TP only)
         PCBSLV_PORT_ID = 0xF        ///< PCB Slave registers
     } p9_port_id_t;
 
@@ -230,23 +232,6 @@ extern "C"
 
     /// P9 MC chiplet SCOM ring ID enumeration
     /// source: tpc_p9_mcslow_top.vhdl
-#ifdef MC_E9022
-    typedef enum
-    {
-        MC_PSCM_RING_ID = 0x0,      ///< PSCOM
-        MC_PERV_RING_ID = 0x1,      ///< PERV
-        MC_MC01_0_RING_ID = 0x2,    ///< MC01_0 / MC23_0
-        MC_MCTRA_0_RING_ID = 0x3,   ///< MCTRA01_0 / MCTRA23_0
-        MC_IOM0_0_RING_ID = 0x4,    ///< IOM01_0 / IOM45_0
-        MC_IOM0_1_RING_ID = 0x5,    ///< IOM01_1 / IOM45_1
-        MC_IOM1_0_RING_ID = 0x6,    ///< IOM01_2 / IOM45_2
-        MC_IOM1_1_RING_ID = 0x7,    ///< IOM01_3 / IOM45_3
-        MC_IOM2_0_RING_ID = 0x8,    ///< IOM23_0 / IOM67_0
-        MC_IOM2_1_RING_ID = 0x9,    ///< IOM23_1 / IOM67_1
-        MC_IOM3_0_RING_ID = 0xa,    ///< IOM23_2 / IOM67_2
-        MC_IOM3_1_RING_ID = 0xb     ///< IOM23_3 / IOM67_3
-    } p9_mc_ring_id_t;
-#else
     typedef enum
     {
         MC_PSCM_RING_ID = 0x0,      ///< PSCOM
@@ -259,7 +244,6 @@ extern "C"
         MC_IOM23_1_RING_ID = 0x7,   ///< IOM23_1 / IOM67_1
         MC_MC01_1_RING_ID = 0x8,    ///< MC01_1 / MC23_1
     } p9_mc_ring_id_t;
-#endif
 
     typedef enum
     {
@@ -338,6 +322,41 @@ extern "C"
         PCI_IOPCI_0_RING_ID = 0x3    ///< IOPCI_0
     } p9_pci_ring_id_t;
 
+    /// P9 PPE GPE ring enumeration (bits 16:21)
+    typedef enum
+    {
+        PPE_SBE_RING_ID  = 0x00,
+        PPE_GPE0_RING_ID = 0x00,
+        PPE_GPE1_RING_ID = 0x08,
+        PPE_GPE2_RING_ID = 0x10,
+        PPE_GPE3_RING_ID = 0x18,
+    } p9_tp_ring_id_t;
+
+    /// Satellite ID for SBE
+    typedef enum
+    {
+        PPE_SBE_SAT_ID = 0x0,
+    } p9_tp_sbe_sat_id_t;
+
+    /// Satellite ID for PPE GPE
+    typedef enum
+    {
+        PPE_GPE_SAT_ID = 0x0,
+    } p9_tp_gpe_sat_id_t;
+
+    /// Satellite ID for PPE CME
+    typedef enum
+    {
+        PPE_CME_SAT_ID = 0x0,
+    } p9_eq_ppe_sat_id_t;
+
+    /// Satellite ID for PPE PB
+    typedef enum
+    {
+        PPE_PB_SAT_ID = 0x0,
+    } p9_n3_ppe_sat_id;
+
+
 //        8             7             6             5             4             3          2         1
 //
 //  |0 1 2 3| |4 5 6 7| |8 9 10 11| |12 13 14 15| |16 17 18 19| |20 21 22 23| |24 25 26 27| |28 29 30 31|
@@ -443,7 +462,7 @@ extern "C"
             /// @retval uint8_t Ring field value
             inline uint8_t get_ring() const
             {
-                return ((iv_addr >> 10) & 0xF);
+                return ((iv_addr >> 10) & 0x3F);
             }
 
             /// @brief Modify SCOM address, update ring field value
@@ -451,8 +470,8 @@ extern "C"
             /// @retval none
             inline void set_ring(const uint8_t i_ring)
             {
-                iv_addr &= 0xFFFFFFFFFFFFC3FFULL;
-                iv_addr |= ((i_ring & 0xF) << 10);
+                iv_addr &= 0xFFFFFFFFFFFF03FFULL;
+                iv_addr |= ((i_ring & 0x3F) << 10);
                 return;
             }
 
diff --git a/src/import/chips/p9/common/scominfo/p9_scominfo.C b/src/import/chips/p9/common/scominfo/p9_scominfo.C
index d1ec2436c..29cbdfbc3 100644
--- a/src/import/chips/p9/common/scominfo/p9_scominfo.C
+++ b/src/import/chips/p9/common/scominfo/p9_scominfo.C
@@ -35,11 +35,11 @@
 
 extern "C"
 {
-
     uint64_t p9_scominfo_createChipUnitScomAddr(const p9ChipUnits_t i_p9CU, const uint8_t i_chipUnitNum,
             const uint64_t i_scomAddr, const uint32_t i_mode)
     {
         p9_scom_addr l_scom(i_scomAddr);
+        uint8_t l_ring = l_scom.get_ring();
 
         //Used to help generate entries for the SCOMdef documentation,
         //These aren't general PIB addresses
@@ -81,8 +81,9 @@ extern "C"
                         l_scom.get_chiplet_id() >= EP00_CHIPLET_ID)
                     {
                         l_scom.set_chiplet_id(EP00_CHIPLET_ID + (i_chipUnitNum / 2));
-                        l_scom.set_ring( ( l_scom.get_ring() - ( l_scom.get_ring() % 2 ) ) +
-                                         ( i_chipUnitNum % 2 ) );
+                        uint8_t l_ringId = (l_scom.get_ring() & 0xF); // Clear bits 16:17
+                        l_ringId = ( l_ringId - ( l_ringId % 2 ) ) + ( i_chipUnitNum % 2 );
+                        l_scom.set_ring( l_ringId & 0xF );
                     }
                     else if (EC23_CHIPLET_ID >= l_scom.get_chiplet_id() &&
                              l_scom.get_chiplet_id() >= EC00_CHIPLET_ID)
@@ -114,10 +115,9 @@ extern "C"
                 case PU_MCA_CHIPUNIT:
                     if (l_scom.get_chiplet_id() == MC01_CHIPLET_ID || l_scom.get_chiplet_id() ==  MC23_CHIPLET_ID)
                     {
-
                         l_scom.set_chiplet_id(MC01_CHIPLET_ID + (i_chipUnitNum / 4));
 
-                        if (l_scom.get_ring() == MC_MC01_0_RING_ID)
+                        if ( (l_scom.get_ring() & 0xF) == MC_MC01_0_RING_ID)
                         {
                             // mc
                             l_scom.set_sat_id( ( l_scom.get_sat_id() - ( l_scom.get_sat_id() % 4 ) ) +
@@ -126,7 +126,7 @@ extern "C"
                         else
                         {
                             // iomc
-                            l_scom.set_ring(MC_IOM01_0_RING_ID + (i_chipUnitNum % 4));
+                            l_scom.set_ring( (MC_IOM01_0_RING_ID + (i_chipUnitNum % 4)) & 0xF );
                         }
                     }
                     else
@@ -152,7 +152,7 @@ extern "C"
                     if (l_scom.get_chiplet_id() == N2_CHIPLET_ID)
                     {
                         // nest
-                        l_scom.set_ring(N2_PCIS0_0_RING_ID + i_chipUnitNum);
+                        l_scom.set_ring( (N2_PCIS0_0_RING_ID + i_chipUnitNum) & 0xF);
                     }
                     else
                     {
@@ -168,12 +168,12 @@ extern "C"
                         // nest
                         if (i_chipUnitNum == 0)
                         {
-                            l_scom.set_ring(N2_PCIS0_0_RING_ID);
+                            l_scom.set_ring(N2_PCIS0_0_RING_ID & 0xF);
                             l_scom.set_sat_id(((l_scom.get_sat_id() < 4) ? (1) : (4)));
                         }
                         else
                         {
-                            l_scom.set_ring(N2_PCIS0_0_RING_ID + (i_chipUnitNum / 3) + 1);
+                            l_scom.set_ring( (N2_PCIS0_0_RING_ID + (i_chipUnitNum / 3) + 1) & 0xF);
                             l_scom.set_sat_id( ((l_scom.get_sat_id() < 4) ? (1) : (4)) +
                                                ((i_chipUnitNum % 2) ? (0) : (1)) +
                                                (2 * (i_chipUnitNum / 5)));
@@ -203,16 +203,109 @@ extern "C"
                     break;
 
                 case PU_XBUS_CHIPUNIT:
-                    if (XB_IOX_2_RING_ID >= l_scom.get_ring() &&
-                        l_scom.get_ring() >= XB_IOX_0_RING_ID)
+
+                    l_ring &= 0xF;
+
+                    if (XB_IOX_2_RING_ID >= l_ring &&
+                        l_ring >= XB_IOX_0_RING_ID)
+                    {
+                        l_scom.set_ring( (XB_IOX_0_RING_ID + i_chipUnitNum) & 0xF);
+                    }
+
+                    else if (XB_PBIOX_2_RING_ID >= l_ring &&
+                             l_ring >= XB_PBIOX_0_RING_ID)
+                    {
+                        l_scom.set_ring( (XB_PBIOX_0_RING_ID + i_chipUnitNum) & 0xF);
+                    }
+
+                    break;
+
+                case PU_SBE_CHIPUNIT:
+                    l_scom.set_chiplet_id(i_chipUnitNum);
+                    break;
+
+                case PU_PPE_CHIPUNIT:
+
+                    // PPE SBE
+                    if (i_chipUnitNum == PPE_SBE_CHIPUNIT_NUM)
+                    {
+                        l_scom.set_chiplet_id(PIB_CHIPLET_ID);
+                        l_scom.set_port(SBE_PORT_ID);
+                        l_scom.set_ring(PPE_SBE_RING_ID);
+                        l_scom.set_sat_id(PPE_SBE_SAT_ID);
+                        l_scom.set_sat_offset(0x0F & l_scom.get_sat_offset());
+                        break;
+                    }
+
+                    // Need to set SAT offset if address is that of PPE SBE
+                    if (l_scom.get_port() == SBE_PORT_ID)
+                    {
+                        // Adjust offset if input address is of SBE
+                        // (ex: 000E0005 --> GPE: xxxxxx1x)
+                        l_scom.set_sat_offset(l_scom.get_sat_offset() | 0x10);
+                    }
+
+                    // PPE GPE
+                    if ( (i_chipUnitNum >= PPE_GPE0_CHIPUNIT_NUM) && (i_chipUnitNum <= PPE_GPE3_CHIPUNIT_NUM) )
+                    {
+                        l_scom.set_chiplet_id(PIB_CHIPLET_ID);
+                        l_scom.set_port(GPE_PORT_ID);
+                        l_scom.set_ring( (i_chipUnitNum - PPE_GPE0_CHIPUNIT_NUM) * 8 );
+                        l_scom.set_sat_id(PPE_GPE_SAT_ID);
+                    }
+
+                    // PPE CME
+                    else if ( (i_chipUnitNum >= PPE_EQ0_CME0_CHIPUNIT_NUM) && (i_chipUnitNum <= PPE_EQ5_CME1_CHIPUNIT_NUM) )
+                    {
+                        if (i_chipUnitNum >= PPE_EQ0_CME1_CHIPUNIT_NUM)
+                        {
+                            l_scom.set_chiplet_id(EP00_CHIPLET_ID +
+                                                  (i_chipUnitNum % PPE_EQ0_CME1_CHIPUNIT_NUM));
+                        }
+                        else
+                        {
+                            l_scom.set_chiplet_id(EP00_CHIPLET_ID +
+                                                  (i_chipUnitNum % PPE_EQ0_CME0_CHIPUNIT_NUM));
+                        }
+
+                        l_scom.set_port(UNIT_PORT_ID);
+                        l_scom.set_ring( ((i_chipUnitNum / PPE_EQ0_CME1_CHIPUNIT_NUM) + 8) & 0xF );
+                        l_scom.set_sat_id(PPE_CME_SAT_ID);
+                    }
+
+                    // PPE IO (XBUS/OBUS/DMI)
+                    else if ( (i_chipUnitNum >= PPE_IO_XBUS_CHIPUNIT_NUM) && (i_chipUnitNum <= PPE_IO1_DMI_CHIPUNIT_NUM) )
+                    {
+                        l_scom.set_chiplet_id( XB_CHIPLET_ID +
+                                               (i_chipUnitNum % PPE_IO_XBUS_CHIPUNIT_NUM) +
+                                               ((i_chipUnitNum / PPE_IO_OB0_CHIPUNIT_NUM) * 2) );
+                        l_scom.set_port(UNIT_PORT_ID);
+
+                        if (i_chipUnitNum == PPE_IO_XBUS_CHIPUNIT_NUM)
+                        {
+                            l_scom.set_ring(XB_IOPPE_0_RING_ID & 0xF);
+                        }
+                        else
+                        {
+                            l_scom.set_ring(OB_PPE_RING_ID & 0xF);
+                        }
+
+                        l_scom.set_sat_id(OB_PPE_SAT_ID); // Same SAT_ID value for XBUS
+                    }
+
+                    // PPE PB
+                    else if ( (i_chipUnitNum >= PPE_PB0_CHIPUNIT_NUM) && (i_chipUnitNum <= PPE_PB2_CHIPUNIT_NUM) )
                     {
-                        l_scom.set_ring(XB_IOX_0_RING_ID + i_chipUnitNum);
+                        l_scom.set_chiplet_id(N3_CHIPLET_ID); // TODO: Need to set ChipID for PB1 and PB2 in Cummulus
+                        l_scom.set_port(UNIT_PORT_ID);
+                        l_scom.set_ring(N3_PB_3_RING_ID & 0xF);
+                        l_scom.set_sat_id(PPE_PB_SAT_ID);
                     }
 
-                    if (XB_PBIOX_2_RING_ID >= l_scom.get_ring() &&
-                        l_scom.get_ring() >= XB_PBIOX_0_RING_ID)
+                    // Invalid i_chipUnitNum
+                    else
                     {
-                        l_scom.set_ring(XB_PBIOX_0_RING_ID + i_chipUnitNum);
+                        l_scom.set_addr(FAILED_TRANSLATION);
                     }
 
                     break;
@@ -449,7 +542,6 @@ extern "C"
                    (l_ring == PCI_PERV_RING_ID)) &&
                   (l_sat_id == PEC_SAT_ID))))
             {
-
                 if ((l_chiplet_id >= PCI0_CHIPLET_ID) && (l_chiplet_id <= PCI2_CHIPLET_ID))
                 {
                     o_chipUnitRelated = true;
@@ -509,7 +601,108 @@ extern "C"
                 o_chipUnitRelated = true;
                 o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_XBUS_CHIPUNIT,
                                             l_ring % 3));
+            }
+
+            // -----------------------------------------------------------------------------
+            // Common 'ppe' registers associated with each pervasive chiplet type
+            // Permit addressing by PPE target type (for all ppe chiplet instances)
+            // -----------------------------------------------------------------------------
+
+            // SBE PM registers
+            //    Port ID = 14
+            if ( (l_port == SBE_PORT_ID) &&
+                 (l_chiplet_id == PIB_CHIPLET_ID) &&
+                 (l_ring == PPE_SBE_RING_ID) &&
+                 (l_sat_id == PPE_SBE_SAT_ID) )
+            {
+                o_chipUnitRelated = true;
+                // PU_SBE_CHIPUNIT
+                o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_SBE_CHIPUNIT,
+                                            l_chiplet_id));
+                // PU_PPE_CHIPUNIT
+                o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_PPE_CHIPUNIT,
+                                            l_chiplet_id));
+            }
 
+            // GPE registers
+            //    Port ID = 1
+            if ( (l_port == GPE_PORT_ID) &&
+                 (l_chiplet_id == PIB_CHIPLET_ID) &&
+                 ( (l_ring == PPE_GPE0_RING_ID) ||
+                   (l_ring == PPE_GPE1_RING_ID) ||
+                   (l_ring == PPE_GPE2_RING_ID) ||
+                   (l_ring == PPE_GPE3_RING_ID) ) &&
+                 (l_sat_id == PPE_GPE_SAT_ID) )
+            {
+                o_chipUnitRelated = true;
+                // PU_PPE_CHIPUNIT
+                o_chipUnitPairing.push_back(p9_chipUnitPairing_t(
+                                                PU_PPE_CHIPUNIT,
+                                                PPE_GPE0_CHIPUNIT_NUM + (l_ring / 8)));
+            }
+
+            // CME registers which can be addressed by PPE target type
+            //    Port ID = 1
+            //    0x10 <= Chiplet ID <= 0x15
+            //    Ring_ID = 0x8 or Ring_ID = 0x9
+            //    SAT_ID = 0
+            if ( (l_port == UNIT_PORT_ID) &&
+                 ((l_chiplet_id >= EP00_CHIPLET_ID) && (l_chiplet_id <= EP05_CHIPLET_ID)) &&
+                 ( (l_ring == EQ_CME_0_RING_ID) || (l_ring == EQ_CME_1_RING_ID) ) &&
+                 (l_sat_id == PPE_CME_SAT_ID) )
+            {
+                o_chipUnitRelated = true;
+                o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_PPE_CHIPUNIT,
+                                            (l_chiplet_id - EP00_CHIPLET_ID) +
+                                            PPE_EQ0_CME0_CHIPUNIT_NUM +
+                                            ((l_ring % 8) * 10)));
+            }
+
+            // PB registers which can be addressed by PPE target type
+            //    Port ID = 1
+            //    Chiplet ID = 0x05
+            //    Ring_ID = 0x9
+            //    SAT_ID = 0
+            if ( (l_port == UNIT_PORT_ID) &&
+                 (l_chiplet_id == N3_CHIPLET_ID) &&
+                 (l_ring == N3_PB_3_RING_ID) &&
+                 (l_sat_id == PPE_PB_SAT_ID) )
+            {
+                o_chipUnitRelated = true;
+                // TODO: Need to update for PB1/PB2 of Cummulus whenever address
+                //       values are available.
+                o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_PPE_CHIPUNIT,
+                                            PPE_PB0_CHIPUNIT_NUM));
+            }
+
+            // XBUS registers which can be addressed by PPE target type (IOPPE)
+            //    Port ID = 1
+            //    Chiplet ID = 0x06
+            //    Ring_ID = 0x2
+            //    SAT_ID = 1
+            if ( (l_port == UNIT_PORT_ID) &&
+                 (l_chiplet_id == XB_CHIPLET_ID) &&
+                 (l_ring == XB_IOPPE_0_RING_ID) &&
+                 (l_sat_id == XB_PPE_SAT_ID) )
+            {
+                o_chipUnitRelated = true;
+                o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_PPE_CHIPUNIT,
+                                            PPE_IO_XBUS_CHIPUNIT_NUM));
+            }
+
+            // OBUS registers which can be addressed by PPE target type (IOPPE)
+            //    Port ID = 1
+            //    Chiplet ID = 0x09, 0x0A, 0x0B, or 0x0C
+            //    Ring_ID = 0x4
+            //    SAT_ID = 1
+            if ( (l_port == UNIT_PORT_ID) &&
+                 ((l_chiplet_id >= OB0_CHIPLET_ID) && (l_chiplet_id <= OB3_CHIPLET_ID)) &&
+                 (l_ring == OB_PPE_RING_ID) &&
+                 (l_sat_id == OB_PPE_SAT_ID) )
+            {
+                o_chipUnitRelated = true;
+                o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_PPE_CHIPUNIT,
+                                            (l_chiplet_id - OB0_CHIPLET_ID) + PPE_IO_OB0_CHIPUNIT_NUM));
             }
         }