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| author | Brian Silver <bsilver@us.ibm.com> | 2016-03-15 08:56:59 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-03-18 09:34:41 -0400 |
| commit | b8e4c142d9ea55ecd7bc0ee499a6ab70ba1ab6a4 (patch) | |
| tree | fff83bb6fd07c0dd05f85b226cc8db745d02ecae /src/import/chips | |
| parent | bce6b464bf2fdbd15aa8302789194fc97a71dab1 (diff) | |
| download | talos-hostboot-b8e4c142d9ea55ecd7bc0ee499a6ab70ba1ab6a4.tar.gz talos-hostboot-b8e4c142d9ea55ecd7bc0ee499a6ab70ba1ab6a4.zip | |
Fix read pointer delay to write to the proper register
Change-Id: I4084b4a01208b4b817f4066df6ec0c325e45c644
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22035
Tested-by: Jenkins Server
Tested-by: Auto Mirror
Tested-by: Hostboot CI
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22037
Tested-by: FSP CI Jenkins
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C index 3e18ebd99..6e68989c9 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C @@ -70,20 +70,20 @@ extern "C" FAPI_TRY( l_mc.setup_xlate_map(p) ); } - // Setup the read_pointer_delay - // TK: Do we need to do this in general or is this a place holder until the - // init file gets here? - { - fapi2::buffer<uint64_t> l_data; - FAPI_TRY( mss::getScom(i_target, MCBIST_MBSEC0Q, l_data) ); - l_data.insertFromRight<MCA_RECR_MBSECCQ_READ_POINTER_DELAY, MCA_RECR_MBSECCQ_READ_POINTER_DELAY_LEN>(0x1); - FAPI_DBG("writing read pointer delay 0x%016lx", l_data); - FAPI_TRY( mss::putScom(i_target, MCBIST_MBSEC0Q, l_data) ); - } - for (auto p : l_mca) { + // Setup the read_pointer_delay + // TK: Do we need to do this in general or is this a place holder until the + // init file gets here? + { + fapi2::buffer<uint64_t> l_data; + FAPI_TRY( mss::getScom(p, MCA_RECR, l_data) ); + l_data.insertFromRight<MCA_RECR_MBSECCQ_READ_POINTER_DELAY, MCA_RECR_MBSECCQ_READ_POINTER_DELAY_LEN>(0x1); + FAPI_DBG("writing read pointer delay 0x%016lx %s", l_data, mss::c_str(p)); + FAPI_TRY( mss::putScom(p, MCA_RECR, l_data) ); + } + // Set the IML Complete bit MBSSQ(3) (SCOM Addr: 0x02011417) to indicate that IML has completed // Can't find MBSSQ or the iml_complete bit - asked Steve. Gary VH created this bit as a scratch // 'you are hre bit' and it was removed for Nimbus. Gary VH asked for it to be put back in. Not |
