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author | Andre Marin <aamarin@us.ibm.com> | 2017-09-05 11:04:23 -0500 |
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committer | Daniel M Crowell <dcrowell@us.ibm.com> | 2019-08-20 08:38:44 -0500 |
commit | a87142ef61562fe484f8000d803ccae4603bbb91 (patch) | |
tree | 2bb60743f9930c6826dd571852bde3b0d611c6d6 /src/import/chips | |
parent | e7de009de612edf353e46301b69f289e08c130a6 (diff) | |
download | talos-hostboot-a87142ef61562fe484f8000d803ccae4603bbb91.tar.gz talos-hostboot-a87142ef61562fe484f8000d803ccae4603bbb91.zip |
Remove logic to disable memory clocks in STR if in PD_AND_STR_CLK_STOP mode
Do not disable memory clocks when in STR if power control mode
PD_AND_STR_CLK_STOP (ie. treat it the same as PD_AND_STR).
Removing EC Chip level check since there isn't a current plan
for a RIT fix.
Change-Id: Ib3728158bd9de46262bd1c21310382ba62a27528
Original-Change-Id: I298561c39a2419ed7f92e90c9eeaf8924fc412bc
CQ:HW416315
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45653
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Michael D. Pardeik <pardeik@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/82434
Reviewed-by: Daniel M Crowell <dcrowell@us.ibm.com>
Tested-by: Daniel M Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips')
-rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C index be4663b4d..86915080f 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C @@ -160,13 +160,6 @@ fapi2::ReturnCode set_str_reg(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_tar break; } - // MCA_MBASTR0Q_CFG_DIS_CLK_IN_STR: Set to 1 for PD_AND_STR_CLK_STOP, otherwise clear the bit - // Only for DD2.0 and above, will not work for DD1.* HW - if( !chip_ec_feature_mss_dis_clk_in_str(i_target) ) - { - l_data.writeBit<MCA_MBASTR0Q_CFG_DIS_CLK_IN_STR>(l_str_enable == PD_AND_STR_CLK_STOP); - } - l_data.insertFromRight<TT::ENTER_STR_TIME_POS, TT::ENTER_STR_TIME_LEN>(ENTER_STR_TIME); FAPI_TRY(mss::putScom(i_target, MCA_MBASTR0Q, l_data), "Error in set_str_reg" ); |