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author | Richard J. Knight <rjknight@us.ibm.com> | 2016-07-26 14:28:54 -0500 |
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committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2017-08-20 09:59:01 -0400 |
commit | 7a59cd81a55eec4aad15c5c1c3814eec9269e9a4 (patch) | |
tree | 62e8b52eb91a292716c85ed0607f79aa93ad2bf9 /src/import/chips | |
parent | 4a787205c9faccb8f31371cc0e53b05d52520b08 (diff) | |
download | talos-hostboot-7a59cd81a55eec4aad15c5c1c3814eec9269e9a4.tar.gz talos-hostboot-7a59cd81a55eec4aad15c5c1c3814eec9269e9a4.zip |
Add sbeError tag to all SBE related error xml files
Change-Id: Id37961b30cd3e430b0a06539f3822665c2d92726
Original-Change-Id: I990940cad75b04131a25ddd1a0aac9dfc10ecf65
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27463
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Santosh S. Puranik <santosh.puranik@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44855
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips')
13 files changed, 44 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_block_wakeup_intr_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_block_wakeup_intr_errors.xml index c23e105d4..f9a76e958 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_block_wakeup_intr_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_block_wakeup_intr_errors.xml @@ -26,6 +26,7 @@ <hwpErrors> <!-- ******************************************************************** --> <hwpError> + <sbeError/> <rc>RC_BLOCK_WAKEUP_INTR_OP</rc> <description>Unknown operation passed to p9_block_wakeup_intr </description> @@ -33,6 +34,7 @@ </hwpError> <!-- ********************************************************************* --> <hwpError> + <sbeError/> <rc>RC_BLOCK_WAKEUP_INTR_CHECK_FAIL</rc> <description>Test of p9_block_wakeup_intr failed. Note: this is NOT a production error definition; used by test infrastructure. diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_dpll_setup_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_dpll_setup_errors.xml index 9b32d2373..c41d931ec 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_dpll_setup_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_dpll_setup_errors.xml @@ -26,6 +26,7 @@ <hwpErrors> <!-- ********************************************************************* --> <hwpError> + <sbeError/> <rc>RC_PMPROC_DPLL_LOCK_TIMEOUT</rc> <description> DPLL is not locking. @@ -56,6 +57,7 @@ </hwpError> <!-- ********************************************************************* --> <hwpError> + <sbeError/> <rc>RC_PMPROC_DPLLCLKSTART_TIMEOUT</rc> <description> dpll clock start timed out. @@ -86,6 +88,7 @@ </hwpError> <!-- ********************************************************************* --> <hwpError> + <sbeError/> <rc>RC_PMPROC_DPLLCLKSTART_FAILED</rc> <description> dpll clock start failed. @@ -94,6 +97,7 @@ </hwpError> <!-- ********************************************************************* --> <hwpError> + <sbeError/> <rc>RC_PMPROC_ANEPCLKSTART_TIMEOUT</rc> <description> anep clock start timed out. diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_startclocks_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_startclocks_errors.xml index 60221feb2..e060a8744 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_startclocks_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_startclocks_errors.xml @@ -26,6 +26,7 @@ <hwpErrors> <!-- ********************************************************************* --> <hwpError> + <sbeError/> <rc>RC_PMPROC_CACHECPLTALIGN_TIMEOUT</rc> <description> cache chiplets alignment timed out. @@ -34,6 +35,7 @@ </hwpError> <!-- ********************************************************************* --> <hwpError> + <sbeError/> <rc>RC_PMPROC_CACHE_XSTOP</rc> <description> cache checkstops. @@ -42,6 +44,7 @@ </hwpError> <!-- ********************************************************************* --> <hwpError> + <sbeError/> <rc>RC_PMPROC_CACHECLKSYNC_TIMEOUT</rc> <description> L2 EXs clock sync done timed out. @@ -50,6 +53,7 @@ </hwpError> <!-- ********************************************************************* --> <hwpError> + <sbeError/> <rc>RC_PMPROC_CACHECLKSTART_FAILED</rc> <description> cache clock start failed. @@ -58,6 +62,7 @@ </hwpError> <!-- ********************************************************************* --> <hwpError> + <sbeError/> <rc>RC_PMPROC_CACHECLKSTART_TIMEOUT</rc> <description> cache clock start timed out. diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_core_startclocks_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_core_startclocks_errors.xml index 25e75af50..e781d46a1 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_core_startclocks_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_core_startclocks_errors.xml @@ -26,6 +26,7 @@ <hwpErrors> <!-- ********************************************************************* --> <hwpError> + <sbeError/> <rc>RC_PMPROC_CORECPLTALIGN_TIMEOUT</rc> <description> core chiplets alignment timed out. @@ -34,6 +35,7 @@ </hwpError> <!-- ********************************************************************* --> <hwpError> + <sbeError/> <rc>RC_PMPROC_QUADCPLTALIGN_FAILED</rc> <description> quad chiplets alignment failed. @@ -42,6 +44,7 @@ </hwpError> <!-- ********************************************************************* --> <hwpError> + <sbeError/> <rc>RC_PMPROC_CORECPLTALIGN_FAILED</rc> <description> core chiplets alignment failed. @@ -50,6 +53,7 @@ </hwpError> <!-- ********************************************************************* --> <hwpError> + <sbeError/> <rc>RC_PMPROC_CORE_XSTOP</rc> <description> core checkstops. @@ -58,6 +62,7 @@ </hwpError> <!-- ********************************************************************* --> <hwpError> + <sbeError/> <rc>RC_PMPROC_CORECLKSYNC_TIMEOUT</rc> <description> core clock sync done timed out. @@ -66,6 +71,7 @@ </hwpError> <!-- ********************************************************************* --> <hwpError> + <sbeError/> <rc>RC_PMPROC_CORECLKSTART_FAILED</rc> <description> core clock start failed. @@ -74,6 +80,7 @@ </hwpError> <!-- ********************************************************************* --> <hwpError> + <sbeError/> <rc>RC_PMPROC_CORECLKSTART_TIMEOUT</rc> <description> core clock start timed out. diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_check_master_stop15_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_check_master_stop15_errors.xml index 3f9648ed9..dc03ef78b 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_check_master_stop15_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_check_master_stop15_errors.xml @@ -25,6 +25,7 @@ <hwpErrors> <!-- ******************************************************************** --> <hwpError> + <sbeError/> <rc>RC_CHECK_MASTER_STOP15_PENDING</rc> <description> Procedure: p9_sbe_check_master_stop15 @@ -37,6 +38,7 @@ </hwpError> <!-- ******************************************************************** --> <hwpError> + <sbeError/> <rc>RC_CHECK_MASTER_STOP15_INVALID_REQUEST_LEVEL</rc> <description> Procedure: p9_sbe_check_master_stop15 @@ -46,6 +48,7 @@ </hwpError> <!-- ******************************************************************** --> <hwpError> + <sbeError/> <rc>RC_CHECK_MASTER_STOP15_INVALID_ACTUAL_LEVEL</rc> <description> Procedure: p9_sbe_check_master_stop15 @@ -55,6 +58,7 @@ </hwpError> <!-- ******************************************************************** --> <hwpError> + <sbeError/> <rc>RC_CHECK_MASTER_STOP15_INVALID_STATE</rc> <description> Procedure: p9_sbe_check_master_stop15 diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_fabricinit_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_fabricinit_errors.xml index 98c64a900..4a4df89bc 100755 --- a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_fabricinit_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_fabricinit_errors.xml @@ -26,6 +26,7 @@ <hwpErrors> <!-- ******************************************************************** --> <hwpError> + <sbeError/> <rc>RC_P9_SBE_FABRICINIT_FBC_STOPPED_ERR</rc> <description> Procedure: p9_sbe_fabricinit @@ -36,6 +37,7 @@ </hwpError> <!-- ******************************************************************** --> <hwpError> + <sbeError/> <rc>RC_P9_SBE_FABRICINIT_FAILED_ERR</rc> <description> Procedure: p9_sbe_fabricinit @@ -47,6 +49,7 @@ </hwpError> <!-- ******************************************************************** --> <hwpError> + <sbeError/> <rc>RC_P9_SBE_FABRICINIT_NO_INIT_ERR</rc> <description> Procedure: p9_sbe_fabricinit diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_gear_switcher_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_gear_switcher_errors.xml index ba0c86396..e2c30ee84 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_gear_switcher_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_gear_switcher_errors.xml @@ -29,6 +29,7 @@ <hwpErrors> <!-- ******************************************************************** --> <hwpError> + <sbeError/> <rc>RC_BUS_STATUS_BUSY_0</rc> <description>Status busy check</description> </hwpError> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_load_bootloader_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_load_bootloader_errors.xml index 332e3bdfa..0429a48f6 100755 --- a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_load_bootloader_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_load_bootloader_errors.xml @@ -27,6 +27,7 @@ <hwpErrors> <!-- ******************************************************************** --> <hwpError> + <sbeError/> <rc>RC_P9_SBE_LOAD_BOOTLOADER_INVALID_TARGET_ADDRESS</rc> <description> Procedure: p9_sbe_load_bootloader @@ -40,6 +41,7 @@ </hwpError> <!-- ******************************************************************** --> <hwpError> + <sbeError/> <rc>RC_P9_SBE_LOAD_BOOTLOADER_INVALID_PAYLOAD_SIZE</rc> <description> Procedure: p9_sbe_load_bootloader @@ -51,6 +53,7 @@ </hwpError> <!-- ******************************************************************** --> <hwpError> + <sbeError/> <rc>RC_P9_MASTER_CORE_NOT_FOUND</rc> <description> Procedure: p9_sbe_load_bootloader diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_mcs_setup_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_mcs_setup_errors.xml index 6fc76c648..5a967d384 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_mcs_setup_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_mcs_setup_errors.xml @@ -25,6 +25,7 @@ <hwpErrors> <!-- ******************************************************************** --> <hwpError> + <sbeError/> <rc>RC_P9_SBE_MCS_SETUP_NO_MC_FOUND_ERR</rc> <description>There is no functional MC chiplet (MCS/MI) present on the master chip</description> <ffdc>CHIP</ffdc> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_npll_setup_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_npll_setup_errors.xml index c522c90c8..15b88735d 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_npll_setup_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_npll_setup_errors.xml @@ -29,24 +29,28 @@ <hwpErrors> <!-- ******************************************************************** --> <hwpError> + <sbeError/> <rc>RC_SS_PLL_LOCK_ERR</rc> <description>Spectrum pll not locked</description> <ffdc>SS_PLL_READ</ffdc> </hwpError> <!-- ******************************************************************** --> <hwpError> + <sbeError/> <rc>RC_CP_FILTER_PLL_LOCK_ERR</rc> <description>CP Filter PLL not locked</description> <ffdc>CP_FILTER_PLL_READ</ffdc> </hwpError> <!-- ******************************************************************** --> <hwpError> + <sbeError/> <rc>RC_NEST_PLL_ERR</rc> <description>Nest PLL not locked</description> <ffdc>NEST_PLL_READ</ffdc> </hwpError> <!-- ******************************************************************** --> <hwpError> + <sbeError/> <rc>RC_IO_FILTER_PLL_LOCK_ERR</rc> <description>IO Filter PLL not locked</description> <ffdc>IO_FILTER_PLL_READ</ffdc> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_select_ex_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_select_ex_errors.xml index 52e7c663f..b857acc54 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_select_ex_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_select_ex_errors.xml @@ -29,16 +29,19 @@ <hwpErrors> <!-- ******************************************************************** --> <hwpError> + <sbeError/> <rc>RC_SBE_SELECT_EX_NO_CORES</rc> <description>No good cores were found in the Partial Good attribures</description> </hwpError> <!-- ******************************************************************** --> <hwpError> + <sbeError/> <rc>RC_SBE_SELECT_EX_NO_EQS</rc> <description>No good cache chiplets were found in the Partial Good attribures</description> </hwpError> <!-- ******************************************************************** --> <hwpError> + <sbeError/> <rc>RC_SBE_SELECT_EX_CORE_EQ_CONFIG_ERROR</rc> <description>Did not find the matching EQ for the first core</description> <ffdc>CORE_NUM</ffdc> @@ -46,6 +49,7 @@ </hwpError> <!-- ******************************************************************** --> <hwpError> + <sbeError/> <rc>RC_SBE_SELECT_EX_NO_CORE_AVAIL_ERROR</rc> <description>No cores are configurable with current partial good and gard settings</description> </hwpError> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_tp_chiplet_init3_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_tp_chiplet_init3_errors.xml index 14ecdc86a..e27d33c5a 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_tp_chiplet_init3_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_tp_chiplet_init3_errors.xml @@ -29,23 +29,27 @@ <hwpErrors> <!-- ******************************************************************** --> <hwpError> + <sbeError/> <rc>RC_XSTOP_ERR</rc> <description>Checkstop bit set in interrupt type reg</description> <ffdc>READ_XSTOP</ffdc> </hwpError> <!-- ******************************************************************** --> <hwpError> + <sbeError/> <rc>RC_CALIBRATION_NOT_DONE</rc> <description>Precision Reference Voltage : Calibration not done</description> </hwpError> <!-- ******************************************************************** --> <hwpError> + <sbeError/> <rc>RC_MF_OSC_ERR</rc> <description>MF Oscillator error active</description> <ffdc>READ_OSCERR_HOLD</ffdc> </hwpError> <!-- ******************************************************************** --> <hwpError> + <sbeError/> <rc>RC_MF_OSC_NOT_TOGGLE</rc> <description>MF Oscillator not toggling</description> <ffdc>READ_SNS1LTH</ffdc> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_tp_switch_gears_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_tp_switch_gears_errors.xml index 45dfa8d3b..c3de1171c 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_tp_switch_gears_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_tp_switch_gears_errors.xml @@ -29,11 +29,13 @@ <hwpErrors> <!-- ******************************************************************** --> <hwpError> + <sbeError/> <rc>RC_BUS_STATUS_BUSY0</rc> <description>Status busy check</description> </hwpError> <!-- ******************************************************************** --> <hwpError> + <sbeError/> <rc>RC_MAGIC_NUMBER_NOT_VALID</rc> <description>Magic number not matching</description> </hwpError> |