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author | Rahul Batra <rbatra@us.ibm.com> | 2018-10-17 14:42:45 -0500 |
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committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2018-10-29 17:40:32 -0500 |
commit | 77fbc86e8ca9b389c20881ef51351433d2f5f5df (patch) | |
tree | 06c7b82a1a1e7ae5cefe336ef6b157b9ee4f4fa4 /src/import/chips | |
parent | 24186bec3e6e98341b79a53020a3a6c606dfd699 (diff) | |
download | talos-hostboot-77fbc86e8ca9b389c20881ef51351433d2f5f5df.tar.gz talos-hostboot-77fbc86e8ca9b389c20881ef51351433d2f5f5df.zip |
PM: Move SGPE/PGPE Region and update QPMR/PPMR(2/4)
2nd commit in series of 4 commits which combined moves SGPE/PGPE
SRAM regions, and also allows to do so easily in future.
Commit 1(Hcode): Adds fields to OCC Complex Shared SRAM for storing SGPE
and PGPE region addresses/size, image header and debug header.
Commit 2(Hostboot): Moves around SGPE/PGPE regions, and adds fields
to QPMR/PPMR for storing SGPE/PGPE region info
Commit 3(Hcode): Populates the newly added SGPE/PGPE region info
fields in QPMR/PPMR
Commit 4(Hostboot): Adds check for QPMR and PPMR fields in the
Hostboot Code
Key_Cronus_Test=PM_REGRESS
Change-Id: I81d65030c31645be38a1c39a80277f2e6bc0cb99
CQ: SW447651
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67641
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Gregory S Still <stillgs@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67653
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips')
3 files changed, 14 insertions, 12 deletions
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H index 9f1ebe5e6..9028ee913 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H @@ -191,7 +191,7 @@ HCD_CONST(SGPE_INSTRUMENTATION_SIZE, (2 * ONE_KB)) HCD_CONST(SGPE_IMAGE_QPMR_OFFSET, (SGPE_BOOT_LOADER_QPMR_OFFSET + SGPE_BOOT_LOADER_SIZE)) -HCD_CONST(SGPE_IMAGE_SIZE, (80 * ONE_KB)) //RTC158543 +HCD_CONST(SGPE_IMAGE_SIZE, (74 * ONE_KB)) //RTC158543 HCD_CONST(SGPE_INT_VECTOR_SIZE, 384) HCD_CONST(SGPE_HCODE_RESET_ADDR_VAL, 0x40) @@ -565,21 +565,18 @@ HCD_CONST(PGPE_FLAG_PHANTOM_HALT_ENABLE, 0x0001) HCD_CONST(PGPE_GLOBAL_PSTATE_PARAM_BLOCK_SIZE, (2 * ONE_KB)) HCD_CONST(PGPE_AUX_TASK_SIZE, (2 * ONE_KB)) -// @todo RTC: 187758 The following is presently hardcoded in PGPE Hcode as -// OCC_SHARED_SRAM_ADDR_LENGTH 2*1024. This should be consolodated -// between platforms in a future release. HCD_CONST(PGPE_OCC_SHARED_SRAM_SIZE, (2 * ONE_KB)) -// @todo RTC: 187760 PGPE_IMAGE_SIZE really should use OCC_SRAM_PGPE_REGION_SIZE from -// p9_hcd_memmap_occ_sram.H. However, this creates a circular dependency. -// where rearrangement is presently prohibitive (OP9010, FIPS910). -HCD_CONST(PGPE_IMAGE_SIZE, ((48 * ONE_KB) - +HCD_CONST(PGPE_IMAGE_SIZE, ((54 * ONE_KB) - PGPE_AUX_TASK_SIZE - PGPE_OCC_SHARED_SRAM_SIZE)) HCD_CONST(PGPE_HCODE_SIZE, (PGPE_IMAGE_SIZE - PGPE_GLOBAL_PSTATE_PARAM_BLOCK_SIZE)) +HCD_CONST(PGPE_DEBUG_PTRS_OFFSET, 0x200) +HCD_CONST(PGPE_DEBUG_PTRS_SIZE, 0x24) + /// Pstate Parameter Block + Pstate Table HCD_CONST(OCC_PSTATE_PARAM_BLOCK_PPMR_OFFSET, (128 * ONE_KB)) diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H index ede7ce4a7..57323d935 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -69,7 +69,7 @@ HCD_CONST(OCC_SRAM_TRACE_BUF_IMP_SIZE, (8 * ONE_KB)) HCD_CONST(OCC_SRAM_IPC_REGION_SIZE, (4 * ONE_KB)) HCD_CONST(OCC_SRAM_GPE0_REGION_SIZE, (60 * ONE_KB)) HCD_CONST(OCC_SRAM_GPE1_REGION_SIZE, (64 * ONE_KB)) -HCD_CONST(OCC_SRAM_PGPE_REGION_SIZE, (48 * ONE_KB )) +HCD_CONST(OCC_SRAM_PGPE_REGION_SIZE, (PGPE_IMAGE_SIZE + PGPE_AUX_TASK_SIZE + PGPE_OCC_SHARED_SRAM_SIZE )) HCD_CONST(OCC_SRAM_SGPE_REGION_SIZE, SGPE_IMAGE_SIZE) HCD_CONST(OCC_SRAM_OCC_REGION_SIZE, (512 * ONE_KB)) @@ -186,7 +186,7 @@ HCD_CONST( OCC_SRAM_SGPE_TRACE_START, (OCC_SRAM_SGPE_HEADER_ADDR + SGPE_HEADER_SIZE)); // PGPE HCD_CONST(OCC_SRAM_PGPE_DASHBOARD_START, - ( OCC_SRAM_PGPE_HEADER_ADDR + PGPE_HEADER_SIZE + SGPE_DEBUG_PTRS_SIZE - 4 )); // For 8B alignment + ( OCC_SRAM_PGPE_HEADER_ADDR + PGPE_HEADER_SIZE + PGPE_DEBUG_PTRS_SIZE - 4 )); // For 8B alignment HCD_CONST( OCC_SRAM_PGPE_DASHBOARD_SIZE, 0xfc ); HCD_CONST( OCC_SRAM_PGPE_TRACE_START, (OCC_SRAM_PGPE_HEADER_ADDR + PGPE_HEADER_SIZE)); diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H index 0e3d59a29..141fb4cb5 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H @@ -105,6 +105,8 @@ HCD_HDR_UINT32( sgpeBootProgCode, 0 ); HCD_HDR_UINT32( sgpeSramImageSize, 0 ); HCD_HDR_UINT32( maxQuadScomRestoreEntry, 0 ); HCD_HDR_UINT32( enable24x7Ima, 0 ); +HCD_HDR_UINT32( sgpeSramRegionStart, 0 ); +HCD_HDR_UINT32( sgpeSramRegionSize, 0 ); HCD_HDR_PAD(512); #ifdef __ASSEMBLER__ .endm @@ -205,6 +207,8 @@ HCD_HDR_UINT32(g_ppmr_aux_task_offset, 0 ); // PGPE Aux Task Offset HCD_HDR_UINT32(g_ppmr_aux_task_length, 0 ); // PGPE Aux Task Length HCD_HDR_UINT32(g_ppmr_doptrace_offset, 0 ); // PGPE Deep Operational Trace Main Memory Buffer Offset HCD_HDR_UINT32(g_ppmr_doptrace_length, 0 ); // PGPEDeep Operation Trace Main Memory Buffer Length +HCD_HDR_UINT32(g_ppmr_pgpe_sram_region_start, 0 ); // +HCD_HDR_UINT32(g_ppmr_pgpe_sram_region_size, 0 ); // HCD_HDR_PAD(0x200); #ifdef __ASSEMBLER__ @@ -360,7 +364,8 @@ HCD_HDR_UINT32(g_pgpe_core_throttle_deassert_cnt, 0 ); // Core throttle de- HCD_HDR_UINT32(g_pgpe_aux_controls, 0 ); // Auxiliary Controls HCD_HDR_UINT32(g_pgpe_doptrace_offset, 0 ); // Deep Operational Trace Main Memory Buffer Offset HCD_HDR_UINT32(g_pgpe_doptrace_length, 0 ); // Deep Opeartional Trace Main Memory Buffer Length - +HCD_HDR_UINT32(g_pgpe_sram_region_start, 0 ); // +HCD_HDR_UINT32(g_pgpe_sram_region_size, 0 ); // #ifdef __ASSEMBLER__ .endm #else |