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authorAmit Kumar <akumar3@us.ibm.com>2016-06-20 01:24:53 -0500
committerDaniel M. Crowell <dcrowell@us.ibm.com>2016-09-25 13:21:24 -0400
commit754955318cdc833def3c8f74037c89e5115324ac (patch)
tree31b202afc1e7dbb39f1fd1dc4ab928a00f7b1911 /src/import/chips
parent273d91b97c16d2af88e3145ccca25256c96c293d (diff)
downloadtalos-hostboot-754955318cdc833def3c8f74037c89e5115324ac.tar.gz
talos-hostboot-754955318cdc833def3c8f74037c89e5115324ac.zip
istep 15 changes
- changes in CME/SGPE hcode for istep15 changes. - merged 23684 changes - sgpe Makefile changes - sgpe_img_edit changes to accept multiple images - changes to get ekb build to do cme and sgpe img edit - Replaced EPM_P9_TUNING with ISTEP15_HACK at few places - More changes to get working on 9067 - Removed trailing whitespace in multiple files which were giving build warnings - Checked in image build wrapper files with new hw_image name plus commented out lines which are being worked out in a separate gerrit id - Added FUSED mode attribute to all base attribute files - Added a first draft of the istep15 perl script in pm tools dir Change-Id: I4f559e041406e09ea1d9376c585c97b8445e8ff8 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26027 Dev-Ready: Gregory S. Still <stillgs@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27329 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips')
-rw-r--r--src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H6
-rwxr-xr-xsrc/import/chips/p9/procedures/hwp/pm/p9_pm_pba_bar_config.C2
-rw-r--r--src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C16
3 files changed, 20 insertions, 4 deletions
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H
index 1d206e976..50022efca 100644
--- a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H
@@ -232,7 +232,11 @@ enum XCR_DEFS
HARD_RESET = 6,
FORCE_HALT = 7
};
-
+enum SLAVE_CONFIG_DEFS
+{
+ CFG_PM_DISABLE = 6,
+ CFG_PM_MUX_DISABLE = 7
+};
} // END OF NAMESPACE p9hcd
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_pba_bar_config.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_pba_bar_config.C
index 5fc92e281..84840be5b 100755
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_pba_bar_config.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_pba_bar_config.C
@@ -202,7 +202,7 @@ fapi2::ReturnCode p9_pm_pba_bar_config (
"Final work_size: 0x%016llX", i_pba_bar_size, l_work_size);
}
- l_finalMask = l_work_size - 1;
+ l_finalMask = (l_work_size - 1) << 20; //shift to align mask 1MB
FAPI_DBG("bar mask: 0x%016llX", l_finalMask);
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C
index c65e26097..9cbbdeb52 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C
@@ -183,6 +183,7 @@ fapi2::ReturnCode stop_gpe_init(
fapi2::buffer<uint64_t> l_xcr;
fapi2::buffer<uint64_t> l_xsr;
fapi2::buffer<uint64_t> l_ivpr;
+ fapi2::buffer<uint64_t> l_slave_cfg;
uint32_t l_ivpr_offset;
uint32_t l_timeout_in_MS = TIMEOUT_COUNT;
@@ -198,6 +199,17 @@ fapi2::ReturnCode stop_gpe_init(
FAPI_INF(" Writing IVPR with 0x%16llX", l_ivpr);
FAPI_TRY(putScom(i_target, PU_GPE3_GPEIVPR_SCOM, l_ivpr));
+ //Read-modify-write on Slave Config register
+ for (auto l_core_target : i_target.getChildren<fapi2::TARGET_TYPE_CORE>())
+ {
+ l_slave_cfg.flush<0>();
+ FAPI_TRY(getScom(l_core_target, EX_SLAVE_CONFIG_REG, l_slave_cfg));
+ l_slave_cfg.clearBit<p9hcd::CFG_PM_DISABLE>();
+ l_slave_cfg.clearBit<p9hcd::CFG_PM_MUX_DISABLE>();
+ FAPI_TRY(putScom(l_core_target, EX_SLAVE_CONFIG_REG, l_slave_cfg));
+ }
+
+
// Program XCR to ACTIVATE SGPE
// @todo 146665 Operations to PPEs should use a p9ppe namespace when created
l_xcr.flush<0>().insertFromRight(p9hcd::HARD_RESET, 1 , 3);
@@ -224,8 +236,8 @@ fapi2::ReturnCode stop_gpe_init(
}
- while((l_occ_flag.getBit<p9hcd::SGPE_ACTIVE>() != 1) &&
- (l_xsr.getBit<p9hcd::HALTED_STATE>() != 1) &&
+ while((!((l_occ_flag.getBit<p9hcd::SGPE_ACTIVE>() == 1) &&
+ (l_xsr.getBit<p9hcd::HALTED_STATE>() == 0))) &&
(--l_timeout_in_MS != 0));
if((l_occ_flag.getBit<p9hcd::SGPE_ACTIVE>() == 1))
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