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authorJoe McGill <jmcgill@us.ibm.com>2017-04-07 08:16:05 -0500
committerDaniel M. Crowell <dcrowell@us.ibm.com>2017-04-13 10:38:28 -0400
commit574d762c9b73bd58dffe76cdaae50af1da8c5c88 (patch)
treef4feba16fdabdea505835838d3d1d6b38d7e5828 /src/import/chips
parentf882d0def567c7d8fc5dea0faf1e3310cc9a674d (diff)
downloadtalos-hostboot-574d762c9b73bd58dffe76cdaae50af1da8c5c88.tar.gz
talos-hostboot-574d762c9b73bd58dffe76cdaae50af1da8c5c88.zip
p9_htm_setup -- cleanup start behavior for multi-chip systems
Current code will generate an error (not propogated back to caller) when attempting to start HTM on p1 via ADU. ADU sequence on p1 fails based on attempting to interlock PB token manager quiesce on slave fabric chip A platform change is also required here to get the correct start behavior. The i_start parameter should be set to true only for the 'last' chip to be initialized in this istep -- this will ensure all chips are properly configured, and the last invocation will trigger all HTMs to begin execution. p9_adu_coherent_utils Issue global HTM start (pmisc) without quiesce + reinit sequence via ADU OPTION reg. Remove TM quiesce interlock as well p9_htm_adu_ctrl Rework return code propogation to correctly return first error Change-Id: Iabac85e4e0341894809464b2d206483170b79f00 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38981 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: CHRISTINA L. GRAVES <clgraves@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38984 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips')
-rw-r--r--src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.C18
-rw-r--r--src/import/chips/p9/procedures/hwp/nest/p9_htm_adu_ctrl.C21
2 files changed, 15 insertions, 24 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.C b/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.C
index a13594784..c2ee515b9 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.C
@@ -484,12 +484,6 @@ extern "C"
// Set AXTYPE = Address only
altd_cmd_reg_data.setBit<ALTD_CMD_ADDRESS_ONLY_BIT>();
- // Set OVERWRITE_PBINIT
- altd_cmd_reg_data.setBit<ALTD_CMD_OVERWRITE_PBINIT_BIT>();
-
- // Set TM_QUIESCE
- altd_cmd_reg_data.setBit<ALTD_CMD_WITH_TM_QUIESCE_BIT>();
-
// ---------------------------------------------------
// PB specific: TTYPE & TSIZE
// ---------------------------------------------------
@@ -501,6 +495,8 @@ extern "C"
// Set TTYPE
altd_cmd_reg_data.insertFromRight<ALTD_CMD_TTYPE_START_BIT,
ALTD_CMD_TTYPE_NUM_BITS>(ALTD_CMD_TTYPE_PB_OPER);
+ // Set TM_QUIESCE
+ altd_cmd_reg_data.setBit<ALTD_CMD_WITH_TM_QUIESCE_BIT>();
if (l_operType == p9_ADU_oper_flag::PB_DIS_OPER)
{
@@ -510,6 +506,9 @@ extern "C"
}
else
{
+ // Set OVERWRITE_PBINIT
+ altd_cmd_reg_data.setBit<ALTD_CMD_OVERWRITE_PBINIT_BIT>();
+
// Set up quiesce
altd_option_reg_data.setBit<FBC_ALTD_WITH_PRE_QUIESCE>();
altd_option_reg_data.insertFromRight<FBC_ALTD_PRE_QUIESCE_COUNT_START_BIT,
@@ -538,8 +537,13 @@ extern "C"
// Set TSIZE
if ( l_transSize == p9_ADU_oper_flag::TSIZE_1 )
{
+ // Set TM_QUIESCE
+ altd_cmd_reg_data.setBit<ALTD_CMD_WITH_TM_QUIESCE_BIT>();
+
altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT,
ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_PMISC_TSIZE_1);
+ // Set quiesce and init around a switch operation in option reg
+ FAPI_TRY(setQuiesceInit(i_target), "setQuiesceInit() returns error");
}
else if ( l_transSize == p9_ADU_oper_flag::TSIZE_2 )
{
@@ -547,8 +551,6 @@ extern "C"
ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_PMISC_TSIZE_2);
}
- // Set quiesce and init around a switch operation in option reg
- FAPI_TRY(setQuiesceInit(i_target), "setQuiesceInit() returns error");
}
}
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_htm_adu_ctrl.C b/src/import/chips/p9/procedures/hwp/nest/p9_htm_adu_ctrl.C
index 1a9d0bafc..af6d69e7a 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_htm_adu_ctrl.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_htm_adu_ctrl.C
@@ -78,16 +78,7 @@ fapi2::ReturnCode aduNHTMControl(
if (l_rc)
{
FAPI_ERR("Error from p9_adu_coherent_manage_lock (acquire all)");
-
- if (l_adu_is_dirty)
- {
- goto adu_reset_unlock;
- }
- else
- {
- fapi2::current_err = l_rc;
- goto fapi_try_exit;
- }
+ goto fapi_try_exit;
}
// NOTE: lock is now held, if an operation fails from this point
@@ -129,7 +120,7 @@ fapi2::ReturnCode aduNHTMControl(
if (l_rc)
{
FAPI_ERR("p9_adu_coherent_status_check() returns error");
- break;
+ goto adu_reset_unlock;
}
if (l_busy_bit_status == true)
@@ -174,13 +165,11 @@ adu_reset_unlock:
// attempt to reset all ADUs and free locks (propogate rc of original fail)
if (l_rc && l_adu_is_dirty)
{
- // save original error for return
- fapi2::current_err = l_rc;
FAPI_INF("Attempting to reset/free lock on all ADUs");
// Unlock ADUs
// ignore return codes
- l_rc = p9_adu_coherent_utils_reset_adu(i_target);
- l_rc = p9_adu_coherent_manage_lock(i_target,
+ (void) p9_adu_coherent_utils_reset_adu(i_target);
+ (void) p9_adu_coherent_manage_lock(i_target,
false, // No lock pick
false, // Lock release
1); // Attempt 1 time
@@ -188,5 +177,5 @@ adu_reset_unlock:
fapi_try_exit:
FAPI_DBG("Exiting");
- return fapi2::current_err;
+ return l_rc;
}
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